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[ARM] 5590/1: Add basic support for ST Nomadik 8815 SoC and evaluation board
[deliverable/linux.git] / arch / arm / mach-ixp4xx / goramo_mlr.c
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11c79740
KH		 1/*
2 * Goramo MultiLink router platform code
3 * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
4 */
5
6#include <linux/delay.h>
7#include <linux/hdlc.h>
8#include <linux/i2c-gpio.h>
9#include <linux/io.h>
10#include <linux/irq.h>
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/serial_8250.h>
14#include <asm/mach-types.h>
15#include <asm/system.h>
16#include <asm/mach/arch.h>
17#include <asm/mach/flash.h>
18#include <asm/mach/pci.h>
19
20#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n)
21#define gpio_irq(n) xgpio_irq(n)
22
23#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
24#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
25#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
26#define SLOT_NEC 0x0E /* IDSEL = AD18 */
27
28#define IRQ_ETHA IRQ_IXP4XX_GPIO4
29#define IRQ_ETHB IRQ_IXP4XX_GPIO5
30#define IRQ_NEC IRQ_IXP4XX_GPIO3
31#define IRQ_MPCI IRQ_IXP4XX_GPIO12
32
33/* GPIO lines */
34#define GPIO_SCL 0
35#define GPIO_SDA 1
36#define GPIO_STR 2
37#define GPIO_HSS0_DCD_N 6
38#define GPIO_HSS1_DCD_N 7
39#define GPIO_HSS0_CTS_N 10
40#define GPIO_HSS1_CTS_N 11
41#define GPIO_HSS1_RTS_N 13
42#define GPIO_HSS0_RTS_N 14
43
44/* Control outputs from 74HC4094 */
45#define CONTROL_HSS0_CLK_INT 0
46#define CONTROL_HSS1_CLK_INT 1
47#define CONTROL_HSS0_DTR_N 2
48#define CONTROL_HSS1_DTR_N 3
49#define CONTROL_EXT 4
50#define CONTROL_AUTO_RESET 5
51#define CONTROL_PCI_RESET_N 6
52#define CONTROL_EEPROM_WC_N 7
53
54/* offsets from start of flash ROM = 0x50000000 */
55#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */
56#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */
57#define CFG_REV 0x4C /* u32 */
58#define CFG_SDRAM_SIZE 0x50 /* u32 */
59#define CFG_SDRAM_CONF 0x54 /* u32 */
60#define CFG_SDRAM_MODE 0x58 /* u32 */
61#define CFG_SDRAM_REFRESH 0x5C /* u32 */
62
63#define CFG_HW_BITS 0x60 /* u32 */
64#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
65#define CFG_HW_HAS_PCI_SLOT 0x00000008
66#define CFG_HW_HAS_ETH0 0x00000010
67#define CFG_HW_HAS_ETH1 0x00000020
68#define CFG_HW_HAS_HSS0 0x00000040
69#define CFG_HW_HAS_HSS1 0x00000080
70#define CFG_HW_HAS_UART0 0x00000100
71#define CFG_HW_HAS_UART1 0x00000200
72#define CFG_HW_HAS_EEPROM 0x00000400
73
74#define FLASH_CMD_READ_ARRAY 0xFF
75#define FLASH_CMD_READ_ID 0x90
76#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */
77
78static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */;
79static u8 control_value;
80
81static void set_scl(u8 value)
82{
83 gpio_line_set(GPIO_SCL, !!value);
84 udelay(3);
85}
86
87static void set_sda(u8 value)
88{
89 gpio_line_set(GPIO_SDA, !!value);
90 udelay(3);
91}
92
93static void set_str(u8 value)
94{
95 gpio_line_set(GPIO_STR, !!value);
96 udelay(3);
97}
98
99static inline void set_control(int line, int value)
100{
101 if (value)
102 control_value |= (1 << line);
103 else
104 control_value &= ~(1 << line);
105}
106
107
108static void output_control(void)
109{
110 int i;
111
112 gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
113 gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
114
115 for (i = 0; i < 8; i++) {
116 set_scl(0);
117 set_sda(control_value & (0x80 >> i)); /* MSB first */
118 set_scl(1); /* active edge */
119 }
120
121 set_str(1);
122 set_str(0);
123
124 set_scl(0);
125 set_sda(1); /* Be ready for START */
126 set_scl(1);
127}
128
129
130static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
131
132static int hss_set_clock(int port, unsigned int clock_type)
133{
134 int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
135
136 switch (clock_type) {
137 case CLOCK_DEFAULT:
138 case CLOCK_EXT:
139 set_control(ctrl_int, 0);
140 output_control();
141 return CLOCK_EXT;
142
143 case CLOCK_INT:
144 set_control(ctrl_int, 1);
145 output_control();
146 return CLOCK_INT;
147
148 default:
149 return -EINVAL;
150 }
151}
152
153static irqreturn_t hss_dcd_irq(int irq, void *pdev)
154{
155 int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N));
156 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
157 set_carrier_cb_tab[port](pdev, !i);
158 return IRQ_HANDLED;
159}
160
161
162static int hss_open(int port, void *pdev,
163 void (*set_carrier_cb)(void *pdev, int carrier))
164{
165 int i, irq;
166
167 if (!port)
168 irq = gpio_irq(GPIO_HSS0_DCD_N);
169 else
170 irq = gpio_irq(GPIO_HSS1_DCD_N);
171
172 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
173 set_carrier_cb(pdev, !i);
174
175 set_carrier_cb_tab[!!port] = set_carrier_cb;
176
177 if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
178 printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
179 irq, i);
180 return i;
181 }
182
183 set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
184 output_control();
185 gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
186 return 0;
187}
188
189static void hss_close(int port, void *pdev)
190{
191 free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N),
192 pdev);
193 set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
194
195 set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
196 output_control();
197 gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
198}
199
200
201/* Flash memory */
202static struct flash_platform_data flash_data = {
203 .map_name = "cfi_probe",
204 .width = 2,
205};
206
207static struct resource flash_resource = {
208 .flags = IORESOURCE_MEM,
209};
210
211static struct platform_device device_flash = {
212 .name = "IXP4XX-Flash",
213 .id = 0,
214 .dev = { .platform_data = &flash_data },
215 .num_resources = 1,
216 .resource = &flash_resource,
217};
218
219
220/* I^2C interface */
221static struct i2c_gpio_platform_data i2c_data = {
222 .sda_pin = GPIO_SDA,
223 .scl_pin = GPIO_SCL,
224};
225
226static struct platform_device device_i2c = {
227 .name = "i2c-gpio",
228 .id = 0,
229 .dev = { .platform_data = &i2c_data },
230};
231
232
233/* IXP425 2 UART ports */
234static struct resource uart_resources[] = {
235 {
236 .start = IXP4XX_UART1_BASE_PHYS,
237 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
238 .flags = IORESOURCE_MEM,
239 },
240 {
241 .start = IXP4XX_UART2_BASE_PHYS,
242 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
243 .flags = IORESOURCE_MEM,
244 }
245};
246
247static struct plat_serial8250_port uart_data[] = {
248 {
249 .mapbase = IXP4XX_UART1_BASE_PHYS,
250 .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
251 REG_OFFSET,
252 .irq = IRQ_IXP4XX_UART1,
253 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
254 .iotype = UPIO_MEM,
255 .regshift = 2,
256 .uartclk = IXP4XX_UART_XTAL,
257 },
258 {
259 .mapbase = IXP4XX_UART2_BASE_PHYS,
260 .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
261 REG_OFFSET,
262 .irq = IRQ_IXP4XX_UART2,
263 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
264 .iotype = UPIO_MEM,
265 .regshift = 2,
266 .uartclk = IXP4XX_UART_XTAL,
267 },
268 { },
269};
270
271static struct platform_device device_uarts = {
272 .name = "serial8250",
273 .id = PLAT8250_DEV_PLATFORM,
274 .dev.platform_data = uart_data,
275 .num_resources = 2,
276 .resource = uart_resources,
277};
278
279
280/* Built-in 10/100 Ethernet MAC interfaces */
281static struct eth_plat_info eth_plat[] = {
282 {
283 .phy = 0,
284 .rxq = 3,
285 .txreadyq = 32,
286 }, {
287 .phy = 1,
288 .rxq = 4,
289 .txreadyq = 33,
290 }
291};
292
293static struct platform_device device_eth_tab[] = {
294 {
295 .name = "ixp4xx_eth",
296 .id = IXP4XX_ETH_NPEB,
297 .dev.platform_data = eth_plat,
298 }, {
299 .name = "ixp4xx_eth",
300 .id = IXP4XX_ETH_NPEC,
301 .dev.platform_data = eth_plat + 1,
302 }
303};
304
305
306/* IXP425 2 synchronous serial ports */
307static struct hss_plat_info hss_plat[] = {
308 {
309 .set_clock = hss_set_clock,
310 .open = hss_open,
311 .close = hss_close,
312 .txreadyq = 34,
313 }, {
314 .set_clock = hss_set_clock,
315 .open = hss_open,
316 .close = hss_close,
317 .txreadyq = 35,
318 }
319};
320
321static struct platform_device device_hss_tab[] = {
322 {
323 .name = "ixp4xx_hss",
324 .id = 0,
325 .dev.platform_data = hss_plat,
326 }, {
327 .name = "ixp4xx_hss",
328 .id = 1,
329 .dev.platform_data = hss_plat + 1,
330 }
331};
332
333
334static struct platform_device *device_tab[6] __initdata = {
335 &device_flash, /* index 0 */
336};
337
338static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
339{
340#ifdef __ARMEB__
341 return __raw_readb(flash + addr);
342#else
343 return __raw_readb(flash + (addr ^ 3));
344#endif
345}
346
347static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
348{
349#ifdef __ARMEB__
350 return __raw_readw(flash + addr);
351#else
352 return __raw_readw(flash + (addr ^ 2));
353#endif
354}
355
356static void __init gmlr_init(void)
357{
358 u8 __iomem *flash;
359 int i, devices = 1; /* flash */
360
361 ixp4xx_sys_init();
362
363 if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
364 printk(KERN_ERR "goramo-mlr: unable to access system"
365 " configuration data\n");
366 else {
367 system_rev = __raw_readl(flash + CFG_REV);
368 hw_bits = __raw_readl(flash + CFG_HW_BITS);
369
370 for (i = 0; i < ETH_ALEN; i++) {
371 eth_plat[0].hwaddr[i] =
372 flash_readb(flash, CFG_ETH0_ADDRESS + i);
373 eth_plat[1].hwaddr[i] =
374 flash_readb(flash, CFG_ETH1_ADDRESS + i);
375 }
376
377 __raw_writew(FLASH_CMD_READ_ID, flash);
378 system_serial_high = flash_readw(flash, FLASH_SER_OFF);
379 system_serial_high <<= 16;
380 system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
381 system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
382 system_serial_low <<= 16;
383 system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
384 __raw_writew(FLASH_CMD_READ_ARRAY, flash);
385
386 iounmap(flash);
387 }
388
389 switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
390 case CFG_HW_HAS_UART0:
391 memset(&uart_data[1], 0, sizeof(uart_data[1]));
392 device_uarts.num_resources = 1;
393 break;
394
395 case CFG_HW_HAS_UART1:
396 device_uarts.dev.platform_data = &uart_data[1];
397 device_uarts.resource = &uart_resources[1];
398 device_uarts.num_resources = 1;
399 break;
400 }
401 if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
402 device_tab[devices++] = &device_uarts; /* max index 1 */
403
404 if (hw_bits & CFG_HW_HAS_ETH0)
405 device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
406 if (hw_bits & CFG_HW_HAS_ETH1)
407 device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
408
409 if (hw_bits & CFG_HW_HAS_HSS0)
410 device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
411 if (hw_bits & CFG_HW_HAS_HSS1)
412 device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
413
414 if (hw_bits & CFG_HW_HAS_EEPROM)
415 device_tab[devices++] = &device_i2c; /* max index 6 */
416
417 gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
418 gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
419 gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT);
420 gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT);
421 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
422 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
423 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
424 set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
425 set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
426
427 set_control(CONTROL_HSS0_DTR_N, 1);
428 set_control(CONTROL_HSS1_DTR_N, 1);
429 set_control(CONTROL_EEPROM_WC_N, 1);
430 set_control(CONTROL_PCI_RESET_N, 1);
431 output_control();
432
433 msleep(1); /* Wait for PCI devices to initialize */
434
435 flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
436 flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
437
438 platform_add_devices(device_tab, devices);
439}
440
441
442#ifdef CONFIG_PCI
443static void __init gmlr_pci_preinit(void)
444{
445 set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW);
446 set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW);
447 set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW);
448 set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW);
449 ixp4xx_pci_preinit();
450}
451
452static void __init gmlr_pci_postinit(void)
453{
454 if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
455 (hw_bits & CFG_HW_USB_PORTS) < 5) {
456 /* need to adjust number of USB ports on NEC chip */
457 u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
458 if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
459 value &= ~7;
460 value |= (hw_bits & CFG_HW_USB_PORTS);
461 ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
462 }
463 }
464}
465
466static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
467{
468 switch(slot) {
469 case SLOT_ETHA: return IRQ_ETHA;
470 case SLOT_ETHB: return IRQ_ETHB;
471 case SLOT_NEC: return IRQ_NEC;
472 default: return IRQ_MPCI;
473 }
474}
475
476static struct hw_pci gmlr_hw_pci __initdata = {
477 .nr_controllers = 1,
478 .preinit = gmlr_pci_preinit,
479 .postinit = gmlr_pci_postinit,
480 .swizzle = pci_std_swizzle,
481 .setup = ixp4xx_setup,
482 .scan = ixp4xx_scan_bus,
483 .map_irq = gmlr_map_irq,
484};
485
486static int __init gmlr_pci_init(void)
487{
488 if (machine_is_goramo_mlr() &&
489 (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
490 pci_common_init(&gmlr_hw_pci);
491 return 0;
492}
493
494subsys_initcall(gmlr_pci_init);
495#endif /* CONFIG_PCI */
496
497
498MACHINE_START(GORAMO_MLR, "MultiLink")
499 /* Maintainer: Krzysztof Halasa */
500 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
501 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
502 .map_io = ixp4xx_map_io,
503 .init_irq = ixp4xx_init_irq,
504 .timer = &ixp4xx_timer,
505 .boot_params = 0x0100,
506 .init_machine = gmlr_init,
507MACHINE_END
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