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1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/ixdp425-setup.c | |
3 | * | |
9bf4d676 | 4 | * IXDP425/IXCDP1100 board-setup |
1da177e4 LT |
5 | * |
6 | * Copyright (C) 2003-2005 MontaVista Software, Inc. | |
7 | * | |
8 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/serial.h> | |
15 | #include <linux/tty.h> | |
16 | #include <linux/serial_8250.h> | |
5a4a2387 | 17 | #include <linux/i2c-gpio.h> |
4ad48b4b VB |
18 | #include <linux/io.h> |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
8029db12 | 22 | #include <linux/delay.h> |
8040dd09 | 23 | #include <linux/gpio.h> |
1da177e4 LT |
24 | #include <asm/types.h> |
25 | #include <asm/setup.h> | |
26 | #include <asm/memory.h> | |
a09e64fb | 27 | #include <mach/hardware.h> |
1da177e4 LT |
28 | #include <asm/mach-types.h> |
29 | #include <asm/irq.h> | |
30 | #include <asm/mach/arch.h> | |
31 | #include <asm/mach/flash.h> | |
32 | ||
9bf4d676 KH |
33 | #define IXDP425_SDA_PIN 7 |
34 | #define IXDP425_SCL_PIN 6 | |
35 | ||
36 | /* NAND Flash pins */ | |
37 | #define IXDP425_NAND_NCE_PIN 12 | |
38 | ||
39 | #define IXDP425_NAND_CMD_BYTE 0x01 | |
40 | #define IXDP425_NAND_ADDR_BYTE 0x02 | |
41 | ||
1da177e4 LT |
42 | static struct flash_platform_data ixdp425_flash_data = { |
43 | .map_name = "cfi_probe", | |
44 | .width = 2, | |
45 | }; | |
46 | ||
47 | static struct resource ixdp425_flash_resource = { | |
1da177e4 LT |
48 | .flags = IORESOURCE_MEM, |
49 | }; | |
50 | ||
51 | static struct platform_device ixdp425_flash = { | |
52 | .name = "IXP4XX-Flash", | |
53 | .id = 0, | |
54 | .dev = { | |
55 | .platform_data = &ixdp425_flash_data, | |
56 | }, | |
57 | .num_resources = 1, | |
58 | .resource = &ixdp425_flash_resource, | |
59 | }; | |
60 | ||
4ad48b4b VB |
61 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
62 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
63 | ||
4ad48b4b VB |
64 | static struct mtd_partition ixdp425_partitions[] = { |
65 | { | |
66 | .name = "ixp400 NAND FS 0", | |
67 | .offset = 0, | |
68 | .size = SZ_8M | |
69 | }, { | |
70 | .name = "ixp400 NAND FS 1", | |
71 | .offset = MTDPART_OFS_APPEND, | |
72 | .size = MTDPART_SIZ_FULL | |
73 | }, | |
74 | }; | |
4ad48b4b VB |
75 | |
76 | static void | |
77 | ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
78 | { | |
c993e095 | 79 | struct nand_chip *this = mtd_to_nand(mtd); |
d9dccc68 | 80 | int offset = (int)nand_get_controller_data(this); |
4ad48b4b VB |
81 | |
82 | if (ctrl & NAND_CTRL_CHANGE) { | |
83 | if (ctrl & NAND_NCE) { | |
8040dd09 | 84 | gpio_set_value(IXDP425_NAND_NCE_PIN, 0); |
4ad48b4b VB |
85 | udelay(5); |
86 | } else | |
8040dd09 | 87 | gpio_set_value(IXDP425_NAND_NCE_PIN, 1); |
4ad48b4b VB |
88 | |
89 | offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; | |
90 | offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; | |
d9dccc68 | 91 | nand_set_controller_data(this, (void *)offset); |
4ad48b4b VB |
92 | } |
93 | ||
94 | if (cmd != NAND_CMD_NONE) | |
95 | writeb(cmd, this->IO_ADDR_W + offset); | |
96 | } | |
97 | ||
98 | static struct platform_nand_data ixdp425_flash_nand_data = { | |
99 | .chip = { | |
ef077179 | 100 | .nr_chips = 1, |
4ad48b4b | 101 | .chip_delay = 30, |
4ad48b4b VB |
102 | .partitions = ixdp425_partitions, |
103 | .nr_partitions = ARRAY_SIZE(ixdp425_partitions), | |
4ad48b4b VB |
104 | }, |
105 | .ctrl = { | |
106 | .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl | |
107 | } | |
108 | }; | |
109 | ||
110 | static struct resource ixdp425_flash_nand_resource = { | |
111 | .flags = IORESOURCE_MEM, | |
112 | }; | |
113 | ||
114 | static struct platform_device ixdp425_flash_nand = { | |
115 | .name = "gen_nand", | |
116 | .id = -1, | |
117 | .dev = { | |
118 | .platform_data = &ixdp425_flash_nand_data, | |
119 | }, | |
120 | .num_resources = 1, | |
121 | .resource = &ixdp425_flash_nand_resource, | |
122 | }; | |
123 | #endif /* CONFIG_MTD_NAND_PLATFORM */ | |
124 | ||
5a4a2387 | 125 | static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = { |
1da177e4 LT |
126 | .sda_pin = IXDP425_SDA_PIN, |
127 | .scl_pin = IXDP425_SCL_PIN, | |
128 | }; | |
129 | ||
5a4a2387 MLJ |
130 | static struct platform_device ixdp425_i2c_gpio = { |
131 | .name = "i2c-gpio", | |
1da177e4 | 132 | .id = 0, |
5a4a2387 MLJ |
133 | .dev = { |
134 | .platform_data = &ixdp425_i2c_gpio_data, | |
1da177e4 | 135 | }, |
1da177e4 LT |
136 | }; |
137 | ||
138 | static struct resource ixdp425_uart_resources[] = { | |
139 | { | |
140 | .start = IXP4XX_UART1_BASE_PHYS, | |
141 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, | |
142 | .flags = IORESOURCE_MEM | |
143 | }, | |
144 | { | |
145 | .start = IXP4XX_UART2_BASE_PHYS, | |
146 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, | |
147 | .flags = IORESOURCE_MEM | |
148 | } | |
149 | }; | |
150 | ||
151 | static struct plat_serial8250_port ixdp425_uart_data[] = { | |
152 | { | |
153 | .mapbase = IXP4XX_UART1_BASE_PHYS, | |
154 | .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, | |
155 | .irq = IRQ_IXP4XX_UART1, | |
8c741ed7 | 156 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
157 | .iotype = UPIO_MEM, |
158 | .regshift = 2, | |
159 | .uartclk = IXP4XX_UART_XTAL, | |
160 | }, | |
161 | { | |
162 | .mapbase = IXP4XX_UART2_BASE_PHYS, | |
163 | .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, | |
a35d6c91 | 164 | .irq = IRQ_IXP4XX_UART2, |
8c741ed7 | 165 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
166 | .iotype = UPIO_MEM, |
167 | .regshift = 2, | |
168 | .uartclk = IXP4XX_UART_XTAL, | |
bcaafbe4 SS |
169 | }, |
170 | { }, | |
1da177e4 LT |
171 | }; |
172 | ||
173 | static struct platform_device ixdp425_uart = { | |
174 | .name = "serial8250", | |
6df29deb | 175 | .id = PLAT8250_DEV_PLATFORM, |
1da177e4 LT |
176 | .dev.platform_data = ixdp425_uart_data, |
177 | .num_resources = 2, | |
178 | .resource = ixdp425_uart_resources | |
179 | }; | |
180 | ||
78225913 RW |
181 | /* Built-in 10/100 Ethernet MAC interfaces */ |
182 | static struct eth_plat_info ixdp425_plat_eth[] = { | |
183 | { | |
184 | .phy = 0, | |
185 | .rxq = 3, | |
186 | .txreadyq = 20, | |
187 | }, { | |
188 | .phy = 1, | |
189 | .rxq = 4, | |
190 | .txreadyq = 21, | |
191 | } | |
192 | }; | |
193 | ||
194 | static struct platform_device ixdp425_eth[] = { | |
195 | { | |
196 | .name = "ixp4xx_eth", | |
197 | .id = IXP4XX_ETH_NPEB, | |
198 | .dev.platform_data = ixdp425_plat_eth, | |
199 | }, { | |
200 | .name = "ixp4xx_eth", | |
201 | .id = IXP4XX_ETH_NPEC, | |
202 | .dev.platform_data = ixdp425_plat_eth + 1, | |
203 | } | |
204 | }; | |
205 | ||
1da177e4 | 206 | static struct platform_device *ixdp425_devices[] __initdata = { |
5a4a2387 | 207 | &ixdp425_i2c_gpio, |
1da177e4 | 208 | &ixdp425_flash, |
4ad48b4b VB |
209 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
210 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
211 | &ixdp425_flash_nand, | |
212 | #endif | |
78225913 RW |
213 | &ixdp425_uart, |
214 | &ixdp425_eth[0], | |
215 | &ixdp425_eth[1], | |
1da177e4 LT |
216 | }; |
217 | ||
1da177e4 LT |
218 | static void __init ixdp425_init(void) |
219 | { | |
220 | ixp4xx_sys_init(); | |
221 | ||
54e269ea DS |
222 | ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
223 | ixdp425_flash_resource.end = | |
224 | IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; | |
1da177e4 | 225 | |
4ad48b4b VB |
226 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
227 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
228 | ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), | |
229 | ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; | |
230 | ||
8040dd09 LW |
231 | gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin"); |
232 | gpio_direction_output(IXDP425_NAND_NCE_PIN, 0); | |
4ad48b4b VB |
233 | |
234 | /* Configure expansion bus for NAND Flash */ | |
235 | *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | | |
236 | IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */ | |
237 | IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */ | |
238 | IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/ | |
239 | IXP4XX_EXP_BUS_WR_EN | | |
240 | IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */ | |
241 | #endif | |
242 | ||
45fba084 RS |
243 | if (cpu_is_ixp43x()) { |
244 | ixdp425_uart.num_resources = 1; | |
245 | ixdp425_uart_data[1].flags = 0; | |
246 | } | |
247 | ||
1da177e4 LT |
248 | platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); |
249 | } | |
250 | ||
b38708fc | 251 | #ifdef CONFIG_ARCH_IXDP425 |
1da177e4 | 252 | MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") |
e9dea0c6 | 253 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 254 | .map_io = ixp4xx_map_io, |
f449588c | 255 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 256 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 257 | .init_time = ixp4xx_timer_init, |
e022c729 | 258 | .atag_offset = 0x100, |
e9dea0c6 | 259 | .init_machine = ixdp425_init, |
7553ee77 NP |
260 | #if defined(CONFIG_PCI) |
261 | .dma_zone_size = SZ_64M, | |
262 | #endif | |
d1b860fb | 263 | .restart = ixp4xx_restart, |
1da177e4 | 264 | MACHINE_END |
e0a20089 | 265 | #endif |
1da177e4 | 266 | |
e0a20089 | 267 | #ifdef CONFIG_MACH_IXDP465 |
1da177e4 | 268 | MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") |
e9dea0c6 | 269 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 270 | .map_io = ixp4xx_map_io, |
f449588c | 271 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 272 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 273 | .init_time = ixp4xx_timer_init, |
e022c729 | 274 | .atag_offset = 0x100, |
e9dea0c6 | 275 | .init_machine = ixdp425_init, |
7553ee77 NP |
276 | #if defined(CONFIG_PCI) |
277 | .dma_zone_size = SZ_64M, | |
278 | #endif | |
1da177e4 | 279 | MACHINE_END |
e0a20089 | 280 | #endif |
1da177e4 | 281 | |
e0a20089 | 282 | #ifdef CONFIG_ARCH_PRPMC1100 |
1da177e4 | 283 | MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") |
e9dea0c6 | 284 | /* Maintainer: MontaVista Software, Inc. */ |
e605ecd7 | 285 | .map_io = ixp4xx_map_io, |
f449588c | 286 | .init_early = ixp4xx_init_early, |
e9dea0c6 | 287 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 288 | .init_time = ixp4xx_timer_init, |
e022c729 | 289 | .atag_offset = 0x100, |
e9dea0c6 | 290 | .init_machine = ixdp425_init, |
7553ee77 NP |
291 | #if defined(CONFIG_PCI) |
292 | .dma_zone_size = SZ_64M, | |
293 | #endif | |
1da177e4 | 294 | MACHINE_END |
e0a20089 | 295 | #endif |
45fba084 RS |
296 | |
297 | #ifdef CONFIG_MACH_KIXRP435 | |
298 | MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") | |
299 | /* Maintainer: MontaVista Software, Inc. */ | |
45fba084 | 300 | .map_io = ixp4xx_map_io, |
f449588c | 301 | .init_early = ixp4xx_init_early, |
45fba084 | 302 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 303 | .init_time = ixp4xx_timer_init, |
e022c729 | 304 | .atag_offset = 0x100, |
45fba084 | 305 | .init_machine = ixdp425_init, |
7553ee77 NP |
306 | #if defined(CONFIG_PCI) |
307 | .dma_zone_size = SZ_64M, | |
308 | #endif | |
45fba084 RS |
309 | MACHINE_END |
310 | #endif |