Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-ixp4xx/ixdp425-setup.c | |
3 | * | |
4 | * IXDP425/IXCDP1100 board-setup | |
5 | * | |
6 | * Copyright (C) 2003-2005 MontaVista Software, Inc. | |
7 | * | |
8 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/serial.h> | |
15 | #include <linux/tty.h> | |
16 | #include <linux/serial_8250.h> | |
54e269ea | 17 | #include <linux/slab.h> |
5a4a2387 | 18 | #include <linux/i2c-gpio.h> |
4ad48b4b VB |
19 | #include <linux/io.h> |
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/mtd/partitions.h> | |
1da177e4 LT |
23 | |
24 | #include <asm/types.h> | |
25 | #include <asm/setup.h> | |
26 | #include <asm/memory.h> | |
27 | #include <asm/hardware.h> | |
28 | #include <asm/mach-types.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/mach/arch.h> | |
31 | #include <asm/mach/flash.h> | |
4ad48b4b | 32 | #include <asm/delay.h> |
1da177e4 | 33 | |
1da177e4 LT |
34 | static struct flash_platform_data ixdp425_flash_data = { |
35 | .map_name = "cfi_probe", | |
36 | .width = 2, | |
37 | }; | |
38 | ||
39 | static struct resource ixdp425_flash_resource = { | |
1da177e4 LT |
40 | .flags = IORESOURCE_MEM, |
41 | }; | |
42 | ||
43 | static struct platform_device ixdp425_flash = { | |
44 | .name = "IXP4XX-Flash", | |
45 | .id = 0, | |
46 | .dev = { | |
47 | .platform_data = &ixdp425_flash_data, | |
48 | }, | |
49 | .num_resources = 1, | |
50 | .resource = &ixdp425_flash_resource, | |
51 | }; | |
52 | ||
4ad48b4b VB |
53 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
54 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
55 | ||
56 | #ifdef CONFIG_MTD_PARTITIONS | |
57 | const char *part_probes[] = { "cmdlinepart", NULL }; | |
58 | ||
59 | static struct mtd_partition ixdp425_partitions[] = { | |
60 | { | |
61 | .name = "ixp400 NAND FS 0", | |
62 | .offset = 0, | |
63 | .size = SZ_8M | |
64 | }, { | |
65 | .name = "ixp400 NAND FS 1", | |
66 | .offset = MTDPART_OFS_APPEND, | |
67 | .size = MTDPART_SIZ_FULL | |
68 | }, | |
69 | }; | |
70 | #endif | |
71 | ||
72 | static void | |
73 | ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
74 | { | |
75 | struct nand_chip *this = mtd->priv; | |
76 | int offset = (int)this->priv; | |
77 | ||
78 | if (ctrl & NAND_CTRL_CHANGE) { | |
79 | if (ctrl & NAND_NCE) { | |
80 | gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW); | |
81 | udelay(5); | |
82 | } else | |
83 | gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH); | |
84 | ||
85 | offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; | |
86 | offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; | |
87 | this->priv = (void *)offset; | |
88 | } | |
89 | ||
90 | if (cmd != NAND_CMD_NONE) | |
91 | writeb(cmd, this->IO_ADDR_W + offset); | |
92 | } | |
93 | ||
94 | static struct platform_nand_data ixdp425_flash_nand_data = { | |
95 | .chip = { | |
96 | .chip_delay = 30, | |
97 | .options = NAND_NO_AUTOINCR, | |
98 | #ifdef CONFIG_MTD_PARTITIONS | |
99 | .part_probe_types = part_probes, | |
100 | .partitions = ixdp425_partitions, | |
101 | .nr_partitions = ARRAY_SIZE(ixdp425_partitions), | |
102 | #endif | |
103 | }, | |
104 | .ctrl = { | |
105 | .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl | |
106 | } | |
107 | }; | |
108 | ||
109 | static struct resource ixdp425_flash_nand_resource = { | |
110 | .flags = IORESOURCE_MEM, | |
111 | }; | |
112 | ||
113 | static struct platform_device ixdp425_flash_nand = { | |
114 | .name = "gen_nand", | |
115 | .id = -1, | |
116 | .dev = { | |
117 | .platform_data = &ixdp425_flash_nand_data, | |
118 | }, | |
119 | .num_resources = 1, | |
120 | .resource = &ixdp425_flash_nand_resource, | |
121 | }; | |
122 | #endif /* CONFIG_MTD_NAND_PLATFORM */ | |
123 | ||
5a4a2387 | 124 | static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = { |
1da177e4 LT |
125 | .sda_pin = IXDP425_SDA_PIN, |
126 | .scl_pin = IXDP425_SCL_PIN, | |
127 | }; | |
128 | ||
5a4a2387 MLJ |
129 | static struct platform_device ixdp425_i2c_gpio = { |
130 | .name = "i2c-gpio", | |
1da177e4 | 131 | .id = 0, |
5a4a2387 MLJ |
132 | .dev = { |
133 | .platform_data = &ixdp425_i2c_gpio_data, | |
1da177e4 | 134 | }, |
1da177e4 LT |
135 | }; |
136 | ||
137 | static struct resource ixdp425_uart_resources[] = { | |
138 | { | |
139 | .start = IXP4XX_UART1_BASE_PHYS, | |
140 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, | |
141 | .flags = IORESOURCE_MEM | |
142 | }, | |
143 | { | |
144 | .start = IXP4XX_UART2_BASE_PHYS, | |
145 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, | |
146 | .flags = IORESOURCE_MEM | |
147 | } | |
148 | }; | |
149 | ||
150 | static struct plat_serial8250_port ixdp425_uart_data[] = { | |
151 | { | |
152 | .mapbase = IXP4XX_UART1_BASE_PHYS, | |
153 | .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, | |
154 | .irq = IRQ_IXP4XX_UART1, | |
8c741ed7 | 155 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
156 | .iotype = UPIO_MEM, |
157 | .regshift = 2, | |
158 | .uartclk = IXP4XX_UART_XTAL, | |
159 | }, | |
160 | { | |
161 | .mapbase = IXP4XX_UART2_BASE_PHYS, | |
162 | .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, | |
a35d6c91 | 163 | .irq = IRQ_IXP4XX_UART2, |
8c741ed7 | 164 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
1da177e4 LT |
165 | .iotype = UPIO_MEM, |
166 | .regshift = 2, | |
167 | .uartclk = IXP4XX_UART_XTAL, | |
bcaafbe4 SS |
168 | }, |
169 | { }, | |
1da177e4 LT |
170 | }; |
171 | ||
172 | static struct platform_device ixdp425_uart = { | |
173 | .name = "serial8250", | |
6df29deb | 174 | .id = PLAT8250_DEV_PLATFORM, |
1da177e4 LT |
175 | .dev.platform_data = ixdp425_uart_data, |
176 | .num_resources = 2, | |
177 | .resource = ixdp425_uart_resources | |
178 | }; | |
179 | ||
180 | static struct platform_device *ixdp425_devices[] __initdata = { | |
5a4a2387 | 181 | &ixdp425_i2c_gpio, |
1da177e4 | 182 | &ixdp425_flash, |
4ad48b4b VB |
183 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
184 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
185 | &ixdp425_flash_nand, | |
186 | #endif | |
1da177e4 LT |
187 | &ixdp425_uart |
188 | }; | |
189 | ||
1da177e4 LT |
190 | static void __init ixdp425_init(void) |
191 | { | |
192 | ixp4xx_sys_init(); | |
193 | ||
54e269ea DS |
194 | ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
195 | ixdp425_flash_resource.end = | |
196 | IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; | |
1da177e4 | 197 | |
4ad48b4b VB |
198 | #if defined(CONFIG_MTD_NAND_PLATFORM) || \ |
199 | defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
200 | ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), | |
201 | ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; | |
202 | ||
203 | gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT); | |
204 | ||
205 | /* Configure expansion bus for NAND Flash */ | |
206 | *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | | |
207 | IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */ | |
208 | IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */ | |
209 | IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/ | |
210 | IXP4XX_EXP_BUS_WR_EN | | |
211 | IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */ | |
212 | #endif | |
213 | ||
45fba084 RS |
214 | if (cpu_is_ixp43x()) { |
215 | ixdp425_uart.num_resources = 1; | |
216 | ixdp425_uart_data[1].flags = 0; | |
217 | } | |
218 | ||
1da177e4 LT |
219 | platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices)); |
220 | } | |
221 | ||
b38708fc | 222 | #ifdef CONFIG_ARCH_IXDP425 |
1da177e4 | 223 | MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") |
e9dea0c6 | 224 | /* Maintainer: MontaVista Software, Inc. */ |
e9dea0c6 RK |
225 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
226 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | |
e605ecd7 | 227 | .map_io = ixp4xx_map_io, |
e9dea0c6 | 228 | .init_irq = ixp4xx_init_irq, |
1da177e4 | 229 | .timer = &ixp4xx_timer, |
e9dea0c6 RK |
230 | .boot_params = 0x0100, |
231 | .init_machine = ixdp425_init, | |
1da177e4 | 232 | MACHINE_END |
e0a20089 | 233 | #endif |
1da177e4 | 234 | |
e0a20089 | 235 | #ifdef CONFIG_MACH_IXDP465 |
1da177e4 | 236 | MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") |
e9dea0c6 | 237 | /* Maintainer: MontaVista Software, Inc. */ |
e9dea0c6 RK |
238 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
239 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | |
e605ecd7 | 240 | .map_io = ixp4xx_map_io, |
e9dea0c6 | 241 | .init_irq = ixp4xx_init_irq, |
1da177e4 | 242 | .timer = &ixp4xx_timer, |
e9dea0c6 RK |
243 | .boot_params = 0x0100, |
244 | .init_machine = ixdp425_init, | |
1da177e4 | 245 | MACHINE_END |
e0a20089 | 246 | #endif |
1da177e4 | 247 | |
e0a20089 | 248 | #ifdef CONFIG_ARCH_PRPMC1100 |
1da177e4 | 249 | MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") |
e9dea0c6 | 250 | /* Maintainer: MontaVista Software, Inc. */ |
e9dea0c6 RK |
251 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, |
252 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | |
e605ecd7 | 253 | .map_io = ixp4xx_map_io, |
e9dea0c6 | 254 | .init_irq = ixp4xx_init_irq, |
1da177e4 | 255 | .timer = &ixp4xx_timer, |
e9dea0c6 RK |
256 | .boot_params = 0x0100, |
257 | .init_machine = ixdp425_init, | |
1da177e4 | 258 | MACHINE_END |
e0a20089 | 259 | #endif |
45fba084 RS |
260 | |
261 | #ifdef CONFIG_MACH_KIXRP435 | |
262 | MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") | |
263 | /* Maintainer: MontaVista Software, Inc. */ | |
264 | .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, | |
265 | .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, | |
266 | .map_io = ixp4xx_map_io, | |
267 | .init_irq = ixp4xx_init_irq, | |
268 | .timer = &ixp4xx_timer, | |
269 | .boot_params = 0x0100, | |
270 | .init_machine = ixdp425_init, | |
271 | MACHINE_END | |
272 | #endif |