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82a96f57 KH |
1 | /* |
2 | * Intel IXP4xx Network Processor Engine driver for Linux | |
3 | * | |
4 | * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of version 2 of the GNU General Public License | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * The code is based on publicly available information: | |
11 | * - Intel IXP4xx Developer's Manual and other e-papers | |
12 | * - Intel IXP400 Access Library Software (BSD license) | |
13 | * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com> | |
14 | * Thanks, Christian. | |
15 | */ | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/firmware.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
a09e64fb | 23 | #include <mach/npe.h> |
82a96f57 KH |
24 | |
25 | #define DEBUG_MSG 0 | |
26 | #define DEBUG_FW 0 | |
27 | ||
28 | #define NPE_COUNT 3 | |
29 | #define MAX_RETRIES 1000 /* microseconds */ | |
30 | #define NPE_42X_DATA_SIZE 0x800 /* in dwords */ | |
31 | #define NPE_46X_DATA_SIZE 0x1000 | |
32 | #define NPE_A_42X_INSTR_SIZE 0x1000 | |
33 | #define NPE_B_AND_C_42X_INSTR_SIZE 0x800 | |
34 | #define NPE_46X_INSTR_SIZE 0x1000 | |
35 | #define REGS_SIZE 0x1000 | |
36 | ||
37 | #define NPE_PHYS_REG 32 | |
38 | ||
39 | #define FW_MAGIC 0xFEEDF00D | |
40 | #define FW_BLOCK_TYPE_INSTR 0x0 | |
41 | #define FW_BLOCK_TYPE_DATA 0x1 | |
42 | #define FW_BLOCK_TYPE_EOF 0xF | |
43 | ||
44 | /* NPE exec status (read) and command (write) */ | |
45 | #define CMD_NPE_STEP 0x01 | |
46 | #define CMD_NPE_START 0x02 | |
47 | #define CMD_NPE_STOP 0x03 | |
48 | #define CMD_NPE_CLR_PIPE 0x04 | |
49 | #define CMD_CLR_PROFILE_CNT 0x0C | |
50 | #define CMD_RD_INS_MEM 0x10 /* instruction memory */ | |
51 | #define CMD_WR_INS_MEM 0x11 | |
52 | #define CMD_RD_DATA_MEM 0x12 /* data memory */ | |
53 | #define CMD_WR_DATA_MEM 0x13 | |
54 | #define CMD_RD_ECS_REG 0x14 /* exec access register */ | |
55 | #define CMD_WR_ECS_REG 0x15 | |
56 | ||
57 | #define STAT_RUN 0x80000000 | |
58 | #define STAT_STOP 0x40000000 | |
59 | #define STAT_CLEAR 0x20000000 | |
60 | #define STAT_ECS_K 0x00800000 /* pipeline clean */ | |
61 | ||
62 | #define NPE_STEVT 0x1B | |
63 | #define NPE_STARTPC 0x1C | |
64 | #define NPE_REGMAP 0x1E | |
65 | #define NPE_CINDEX 0x1F | |
66 | ||
67 | #define INSTR_WR_REG_SHORT 0x0000C000 | |
68 | #define INSTR_WR_REG_BYTE 0x00004000 | |
69 | #define INSTR_RD_FIFO 0x0F888220 | |
70 | #define INSTR_RESET_MBOX 0x0FAC8210 | |
71 | ||
72 | #define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ | |
73 | #define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ | |
74 | #define ECS_BG_CTXT_REG_2 0x02 | |
75 | #define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ | |
76 | #define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ | |
77 | #define ECS_PRI_1_CTXT_REG_2 0x06 | |
78 | #define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ | |
79 | #define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ | |
80 | #define ECS_PRI_2_CTXT_REG_2 0x0A | |
81 | #define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ | |
82 | #define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ | |
83 | #define ECS_DBG_CTXT_REG_2 0x0E | |
84 | #define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ | |
85 | ||
86 | #define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ | |
87 | #define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ | |
88 | #define ECS_REG_0_LDUR_BITS 8 | |
89 | #define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ | |
90 | #define ECS_REG_1_CCTXT_BITS 16 | |
91 | #define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ | |
92 | #define ECS_REG_1_SELCTXT_BITS 0 | |
93 | #define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ | |
94 | #define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ | |
95 | #define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ | |
96 | ||
97 | /* NPE watchpoint_fifo register bit */ | |
98 | #define WFIFO_VALID 0x80000000 | |
99 | ||
100 | /* NPE messaging_status register bit definitions */ | |
101 | #define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ | |
102 | #define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ | |
103 | #define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ | |
104 | #define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ | |
105 | #define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ | |
106 | #define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ | |
107 | #define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ | |
108 | #define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ | |
109 | ||
110 | /* NPE messaging_control register bit definitions */ | |
111 | #define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ | |
112 | #define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ | |
113 | #define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ | |
114 | #define MSGCTL_IN_FIFO_WRITE 0x02000000 | |
115 | ||
116 | /* NPE mailbox_status value for reset */ | |
117 | #define RESET_MBOX_STAT 0x0000F0F0 | |
118 | ||
05cd3db0 TG |
119 | #define NPE_A_FIRMWARE "NPE-A" |
120 | #define NPE_B_FIRMWARE "NPE-B" | |
121 | #define NPE_C_FIRMWARE "NPE-C" | |
122 | ||
123 | const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE }; | |
82a96f57 KH |
124 | |
125 | #define print_npe(pri, npe, fmt, ...) \ | |
126 | printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) | |
127 | ||
128 | #if DEBUG_MSG | |
129 | #define debug_msg(npe, fmt, ...) \ | |
130 | print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) | |
131 | #else | |
132 | #define debug_msg(npe, fmt, ...) | |
133 | #endif | |
134 | ||
135 | static struct { | |
136 | u32 reg, val; | |
137 | } ecs_reset[] = { | |
138 | { ECS_BG_CTXT_REG_0, 0xA0000000 }, | |
139 | { ECS_BG_CTXT_REG_1, 0x01000000 }, | |
140 | { ECS_BG_CTXT_REG_2, 0x00008000 }, | |
141 | { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, | |
142 | { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, | |
143 | { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, | |
144 | { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, | |
145 | { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, | |
146 | { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, | |
147 | { ECS_DBG_CTXT_REG_0, 0x20000000 }, | |
148 | { ECS_DBG_CTXT_REG_1, 0x00000000 }, | |
149 | { ECS_DBG_CTXT_REG_2, 0x001E0000 }, | |
150 | { ECS_INSTRUCT_REG, 0x1003C00F }, | |
151 | }; | |
152 | ||
153 | static struct npe npe_tab[NPE_COUNT] = { | |
154 | { | |
155 | .id = 0, | |
156 | .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT, | |
157 | .regs_phys = IXP4XX_NPEA_BASE_PHYS, | |
158 | }, { | |
159 | .id = 1, | |
160 | .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT, | |
161 | .regs_phys = IXP4XX_NPEB_BASE_PHYS, | |
162 | }, { | |
163 | .id = 2, | |
164 | .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT, | |
165 | .regs_phys = IXP4XX_NPEC_BASE_PHYS, | |
166 | } | |
167 | }; | |
168 | ||
169 | int npe_running(struct npe *npe) | |
170 | { | |
171 | return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; | |
172 | } | |
173 | ||
174 | static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) | |
175 | { | |
176 | __raw_writel(data, &npe->regs->exec_data); | |
177 | __raw_writel(addr, &npe->regs->exec_addr); | |
178 | __raw_writel(cmd, &npe->regs->exec_status_cmd); | |
179 | } | |
180 | ||
181 | static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) | |
182 | { | |
183 | __raw_writel(addr, &npe->regs->exec_addr); | |
184 | __raw_writel(cmd, &npe->regs->exec_status_cmd); | |
185 | /* Iintroduce extra read cycles after issuing read command to NPE | |
186 | so that we read the register after the NPE has updated it. | |
187 | This is to overcome race condition between XScale and NPE */ | |
188 | __raw_readl(&npe->regs->exec_data); | |
189 | __raw_readl(&npe->regs->exec_data); | |
190 | return __raw_readl(&npe->regs->exec_data); | |
191 | } | |
192 | ||
193 | static void npe_clear_active(struct npe *npe, u32 reg) | |
194 | { | |
195 | u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); | |
196 | npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); | |
197 | } | |
198 | ||
199 | static void npe_start(struct npe *npe) | |
200 | { | |
201 | /* ensure only Background Context Stack Level is active */ | |
202 | npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); | |
203 | npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); | |
204 | npe_clear_active(npe, ECS_DBG_CTXT_REG_0); | |
205 | ||
206 | __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); | |
207 | __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); | |
208 | } | |
209 | ||
210 | static void npe_stop(struct npe *npe) | |
211 | { | |
212 | __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); | |
213 | __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ | |
214 | } | |
215 | ||
216 | static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, | |
217 | u32 ldur) | |
218 | { | |
219 | u32 wc; | |
220 | int i; | |
221 | ||
222 | /* set the Active bit, and the LDUR, in the debug level */ | |
223 | npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, | |
224 | ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); | |
225 | ||
226 | /* set CCTXT at ECS DEBUG L3 to specify in which context to execute | |
227 | the instruction, and set SELCTXT at ECS DEBUG Level to specify | |
228 | which context store to access. | |
229 | Debug ECS Level Reg 1 has form 0x000n000n, where n = context number | |
230 | */ | |
231 | npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, | |
232 | (ctx << ECS_REG_1_CCTXT_BITS) | | |
233 | (ctx << ECS_REG_1_SELCTXT_BITS)); | |
234 | ||
235 | /* clear the pipeline */ | |
236 | __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); | |
237 | ||
238 | /* load NPE instruction into the instruction register */ | |
239 | npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); | |
240 | ||
241 | /* we need this value later to wait for completion of NPE execution | |
242 | step */ | |
243 | wc = __raw_readl(&npe->regs->watch_count); | |
244 | ||
245 | /* issue a Step One command via the Execution Control register */ | |
246 | __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); | |
247 | ||
248 | /* Watch Count register increments when NPE completes an instruction */ | |
249 | for (i = 0; i < MAX_RETRIES; i++) { | |
250 | if (wc != __raw_readl(&npe->regs->watch_count)) | |
251 | return 0; | |
252 | udelay(1); | |
253 | } | |
254 | ||
255 | print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); | |
256 | return -ETIMEDOUT; | |
257 | } | |
258 | ||
259 | static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, | |
260 | u8 val, u32 ctx) | |
261 | { | |
262 | /* here we build the NPE assembler instruction: mov8 d0, #0 */ | |
263 | u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ | |
264 | addr << 9 | /* base Operand */ | |
265 | (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ | |
266 | (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ | |
267 | return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ | |
268 | } | |
269 | ||
270 | static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, | |
271 | u16 val, u32 ctx) | |
272 | { | |
273 | /* here we build the NPE assembler instruction: mov16 d0, #0 */ | |
274 | u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ | |
275 | addr << 9 | /* base Operand */ | |
276 | (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ | |
277 | (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ | |
278 | return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ | |
279 | } | |
280 | ||
281 | static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, | |
282 | u32 val, u32 ctx) | |
283 | { | |
284 | /* write in 16 bit steps first the high and then the low value */ | |
285 | if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) | |
286 | return -ETIMEDOUT; | |
287 | return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); | |
288 | } | |
289 | ||
290 | static int npe_reset(struct npe *npe) | |
291 | { | |
292 | u32 val, ctl, exec_count, ctx_reg2; | |
293 | int i; | |
294 | ||
295 | ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & | |
296 | 0x3F3FFFFF; | |
297 | ||
298 | /* disable parity interrupt */ | |
299 | __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); | |
300 | ||
301 | /* pre exec - debug instruction */ | |
302 | /* turn off the halt bit by clearing Execution Count register. */ | |
303 | exec_count = __raw_readl(&npe->regs->exec_count); | |
304 | __raw_writel(0, &npe->regs->exec_count); | |
305 | /* ensure that IF and IE are on (temporarily), so that we don't end up | |
306 | stepping forever */ | |
307 | ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); | |
308 | npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | | |
309 | ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); | |
310 | ||
311 | /* clear the FIFOs */ | |
312 | while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) | |
313 | ; | |
314 | while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) | |
315 | /* read from the outFIFO until empty */ | |
316 | print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", | |
317 | __raw_readl(&npe->regs->in_out_fifo)); | |
318 | ||
319 | while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) | |
320 | /* step execution of the NPE intruction to read inFIFO using | |
321 | the Debug Executing Context stack */ | |
322 | if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) | |
323 | return -ETIMEDOUT; | |
324 | ||
325 | /* reset the mailbox reg from the XScale side */ | |
326 | __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); | |
327 | /* from NPE side */ | |
328 | if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) | |
329 | return -ETIMEDOUT; | |
330 | ||
331 | /* Reset the physical registers in the NPE register file */ | |
332 | for (val = 0; val < NPE_PHYS_REG; val++) { | |
333 | if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) | |
334 | return -ETIMEDOUT; | |
335 | /* address is either 0 or 4 */ | |
336 | if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) | |
337 | return -ETIMEDOUT; | |
338 | } | |
339 | ||
340 | /* Reset the context store = each context's Context Store registers */ | |
341 | ||
342 | /* Context 0 has no STARTPC. Instead, this value is used to set NextPC | |
343 | for Background ECS, to set where NPE starts executing code */ | |
344 | val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); | |
345 | val &= ~ECS_REG_0_NEXTPC_MASK; | |
346 | val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; | |
347 | npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); | |
348 | ||
349 | for (i = 0; i < 16; i++) { | |
350 | if (i) { /* Context 0 has no STEVT nor STARTPC */ | |
351 | /* STEVT = off, 0x80 */ | |
352 | if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) | |
353 | return -ETIMEDOUT; | |
354 | if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) | |
355 | return -ETIMEDOUT; | |
356 | } | |
357 | /* REGMAP = d0->p0, d8->p2, d16->p4 */ | |
358 | if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) | |
359 | return -ETIMEDOUT; | |
360 | if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) | |
361 | return -ETIMEDOUT; | |
362 | } | |
363 | ||
364 | /* post exec */ | |
365 | /* clear active bit in debug level */ | |
366 | npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); | |
367 | /* clear the pipeline */ | |
368 | __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); | |
369 | /* restore previous values */ | |
370 | __raw_writel(exec_count, &npe->regs->exec_count); | |
371 | npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); | |
372 | ||
373 | /* write reset values to Execution Context Stack registers */ | |
374 | for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) | |
375 | npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, | |
376 | ecs_reset[val].val); | |
377 | ||
378 | /* clear the profile counter */ | |
379 | __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); | |
380 | ||
381 | __raw_writel(0, &npe->regs->exec_count); | |
382 | __raw_writel(0, &npe->regs->action_points[0]); | |
383 | __raw_writel(0, &npe->regs->action_points[1]); | |
384 | __raw_writel(0, &npe->regs->action_points[2]); | |
385 | __raw_writel(0, &npe->regs->action_points[3]); | |
386 | __raw_writel(0, &npe->regs->watch_count); | |
387 | ||
388 | val = ixp4xx_read_feature_bits(); | |
389 | /* reset the NPE */ | |
390 | ixp4xx_write_feature_bits(val & | |
391 | ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); | |
82a96f57 KH |
392 | /* deassert reset */ |
393 | ixp4xx_write_feature_bits(val | | |
394 | (IXP4XX_FEATURE_RESET_NPEA << npe->id)); | |
395 | for (i = 0; i < MAX_RETRIES; i++) { | |
396 | if (ixp4xx_read_feature_bits() & | |
397 | (IXP4XX_FEATURE_RESET_NPEA << npe->id)) | |
398 | break; /* NPE is back alive */ | |
399 | udelay(1); | |
400 | } | |
401 | if (i == MAX_RETRIES) | |
402 | return -ETIMEDOUT; | |
403 | ||
404 | npe_stop(npe); | |
405 | ||
406 | /* restore NPE configuration bus Control Register - parity settings */ | |
407 | __raw_writel(ctl, &npe->regs->messaging_control); | |
408 | return 0; | |
409 | } | |
410 | ||
411 | ||
412 | int npe_send_message(struct npe *npe, const void *msg, const char *what) | |
413 | { | |
414 | const u32 *send = msg; | |
415 | int cycles = 0; | |
416 | ||
417 | debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", | |
418 | what, send[0], send[1]); | |
419 | ||
420 | if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { | |
421 | debug_msg(npe, "NPE input FIFO not empty\n"); | |
422 | return -EIO; | |
423 | } | |
424 | ||
425 | __raw_writel(send[0], &npe->regs->in_out_fifo); | |
426 | ||
427 | if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { | |
428 | debug_msg(npe, "NPE input FIFO full\n"); | |
429 | return -EIO; | |
430 | } | |
431 | ||
432 | __raw_writel(send[1], &npe->regs->in_out_fifo); | |
433 | ||
434 | while ((cycles < MAX_RETRIES) && | |
435 | (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { | |
436 | udelay(1); | |
437 | cycles++; | |
438 | } | |
439 | ||
440 | if (cycles == MAX_RETRIES) { | |
441 | debug_msg(npe, "Timeout sending message\n"); | |
442 | return -ETIMEDOUT; | |
443 | } | |
444 | ||
dac2f83f | 445 | #if DEBUG_MSG > 1 |
82a96f57 | 446 | debug_msg(npe, "Sending a message took %i cycles\n", cycles); |
dac2f83f | 447 | #endif |
82a96f57 KH |
448 | return 0; |
449 | } | |
450 | ||
451 | int npe_recv_message(struct npe *npe, void *msg, const char *what) | |
452 | { | |
453 | u32 *recv = msg; | |
454 | int cycles = 0, cnt = 0; | |
455 | ||
456 | debug_msg(npe, "Trying to receive message %s\n", what); | |
457 | ||
458 | while (cycles < MAX_RETRIES) { | |
459 | if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { | |
460 | recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); | |
461 | if (cnt == 2) | |
462 | break; | |
463 | } else { | |
464 | udelay(1); | |
465 | cycles++; | |
466 | } | |
467 | } | |
468 | ||
469 | switch(cnt) { | |
470 | case 1: | |
471 | debug_msg(npe, "Received [%08X]\n", recv[0]); | |
472 | break; | |
473 | case 2: | |
474 | debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); | |
475 | break; | |
476 | } | |
477 | ||
478 | if (cycles == MAX_RETRIES) { | |
479 | debug_msg(npe, "Timeout waiting for message\n"); | |
480 | return -ETIMEDOUT; | |
481 | } | |
482 | ||
dac2f83f | 483 | #if DEBUG_MSG > 1 |
82a96f57 | 484 | debug_msg(npe, "Receiving a message took %i cycles\n", cycles); |
dac2f83f | 485 | #endif |
82a96f57 KH |
486 | return 0; |
487 | } | |
488 | ||
489 | int npe_send_recv_message(struct npe *npe, void *msg, const char *what) | |
490 | { | |
491 | int result; | |
492 | u32 *send = msg, recv[2]; | |
493 | ||
494 | if ((result = npe_send_message(npe, msg, what)) != 0) | |
495 | return result; | |
496 | if ((result = npe_recv_message(npe, recv, what)) != 0) | |
497 | return result; | |
498 | ||
499 | if ((recv[0] != send[0]) || (recv[1] != send[1])) { | |
500 | debug_msg(npe, "Message %s: unexpected message received\n", | |
501 | what); | |
502 | return -EIO; | |
503 | } | |
504 | return 0; | |
505 | } | |
506 | ||
507 | ||
508 | int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |
509 | { | |
510 | const struct firmware *fw_entry; | |
511 | ||
512 | struct dl_block { | |
513 | u32 type; | |
514 | u32 offset; | |
515 | } *blk; | |
516 | ||
517 | struct dl_image { | |
518 | u32 magic; | |
519 | u32 id; | |
520 | u32 size; | |
521 | union { | |
522 | u32 data[0]; | |
523 | struct dl_block blocks[0]; | |
524 | }; | |
525 | } *image; | |
526 | ||
527 | struct dl_codeblock { | |
528 | u32 npe_addr; | |
529 | u32 size; | |
530 | u32 data[0]; | |
531 | } *cb; | |
532 | ||
533 | int i, j, err, data_size, instr_size, blocks, table_end; | |
534 | u32 cmd; | |
535 | ||
536 | if ((err = request_firmware(&fw_entry, name, dev)) != 0) | |
537 | return err; | |
538 | ||
539 | err = -EINVAL; | |
540 | if (fw_entry->size < sizeof(struct dl_image)) { | |
541 | print_npe(KERN_ERR, npe, "incomplete firmware file\n"); | |
542 | goto err; | |
543 | } | |
544 | image = (struct dl_image*)fw_entry->data; | |
545 | ||
546 | #if DEBUG_FW | |
547 | print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", | |
548 | image->magic, image->id, image->size, image->size * 4); | |
549 | #endif | |
550 | ||
551 | if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ | |
552 | image->id = swab32(image->id); | |
553 | image->size = swab32(image->size); | |
554 | } else if (image->magic != FW_MAGIC) { | |
555 | print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", | |
556 | image->magic); | |
557 | goto err; | |
558 | } | |
559 | if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { | |
560 | print_npe(KERN_ERR, npe, | |
561 | "inconsistent size of firmware file\n"); | |
562 | goto err; | |
563 | } | |
564 | if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { | |
565 | print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); | |
566 | goto err; | |
567 | } | |
568 | if (image->magic == swab32(FW_MAGIC)) | |
569 | for (i = 0; i < image->size; i++) | |
570 | image->data[i] = swab32(image->data[i]); | |
571 | ||
5ca328d2 KH |
572 | if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { |
573 | print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " | |
82a96f57 KH |
574 | "IXP42x\n"); |
575 | goto err; | |
576 | } | |
577 | ||
578 | if (npe_running(npe)) { | |
579 | print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " | |
580 | "already running\n"); | |
581 | err = -EBUSY; | |
582 | goto err; | |
583 | } | |
584 | #if 0 | |
585 | npe_stop(npe); | |
586 | npe_reset(npe); | |
587 | #endif | |
588 | ||
589 | print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " | |
590 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, | |
591 | (image->id >> 8) & 0xFF, image->id & 0xFF); | |
592 | ||
5ca328d2 | 593 | if (cpu_is_ixp42x()) { |
82a96f57 KH |
594 | if (!npe->id) |
595 | instr_size = NPE_A_42X_INSTR_SIZE; | |
596 | else | |
597 | instr_size = NPE_B_AND_C_42X_INSTR_SIZE; | |
598 | data_size = NPE_42X_DATA_SIZE; | |
599 | } else { | |
600 | instr_size = NPE_46X_INSTR_SIZE; | |
601 | data_size = NPE_46X_DATA_SIZE; | |
602 | } | |
603 | ||
604 | for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; | |
605 | blocks++) | |
606 | if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) | |
607 | break; | |
608 | if (blocks * sizeof(struct dl_block) / 4 >= image->size) { | |
609 | print_npe(KERN_INFO, npe, "firmware EOF block marker not " | |
610 | "found\n"); | |
611 | goto err; | |
612 | } | |
613 | ||
614 | #if DEBUG_FW | |
615 | print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); | |
616 | #endif | |
617 | ||
618 | table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; | |
619 | for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { | |
620 | if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 | |
621 | || blk->offset < table_end) { | |
622 | print_npe(KERN_INFO, npe, "invalid offset 0x%X of " | |
623 | "firmware block #%i\n", blk->offset, i); | |
624 | goto err; | |
625 | } | |
626 | ||
627 | cb = (struct dl_codeblock*)&image->data[blk->offset]; | |
628 | if (blk->type == FW_BLOCK_TYPE_INSTR) { | |
629 | if (cb->npe_addr + cb->size > instr_size) | |
630 | goto too_big; | |
631 | cmd = CMD_WR_INS_MEM; | |
632 | } else if (blk->type == FW_BLOCK_TYPE_DATA) { | |
633 | if (cb->npe_addr + cb->size > data_size) | |
634 | goto too_big; | |
635 | cmd = CMD_WR_DATA_MEM; | |
636 | } else { | |
637 | print_npe(KERN_INFO, npe, "invalid firmware block #%i " | |
638 | "type 0x%X\n", i, blk->type); | |
639 | goto err; | |
640 | } | |
641 | if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { | |
642 | print_npe(KERN_INFO, npe, "firmware block #%i doesn't " | |
643 | "fit in firmware image: type %c, start 0x%X," | |
644 | " length 0x%X\n", i, | |
645 | blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', | |
646 | cb->npe_addr, cb->size); | |
647 | goto err; | |
648 | } | |
649 | ||
650 | for (j = 0; j < cb->size; j++) | |
651 | npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); | |
652 | } | |
653 | ||
654 | npe_start(npe); | |
655 | if (!npe_running(npe)) | |
656 | print_npe(KERN_ERR, npe, "unable to start\n"); | |
657 | release_firmware(fw_entry); | |
658 | return 0; | |
659 | ||
660 | too_big: | |
661 | print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " | |
662 | "memory: type %c, start 0x%X, length 0x%X\n", i, | |
663 | blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', | |
664 | cb->npe_addr, cb->size); | |
665 | err: | |
666 | release_firmware(fw_entry); | |
667 | return err; | |
668 | } | |
669 | ||
670 | ||
efec194f | 671 | struct npe *npe_request(unsigned id) |
82a96f57 KH |
672 | { |
673 | if (id < NPE_COUNT) | |
674 | if (npe_tab[id].valid) | |
675 | if (try_module_get(THIS_MODULE)) | |
676 | return &npe_tab[id]; | |
677 | return NULL; | |
678 | } | |
679 | ||
680 | void npe_release(struct npe *npe) | |
681 | { | |
682 | module_put(THIS_MODULE); | |
683 | } | |
684 | ||
685 | ||
686 | static int __init npe_init_module(void) | |
687 | { | |
688 | ||
689 | int i, found = 0; | |
690 | ||
691 | for (i = 0; i < NPE_COUNT; i++) { | |
692 | struct npe *npe = &npe_tab[i]; | |
693 | if (!(ixp4xx_read_feature_bits() & | |
694 | (IXP4XX_FEATURE_RESET_NPEA << i))) | |
695 | continue; /* NPE already disabled or not present */ | |
696 | if (!(npe->mem_res = request_mem_region(npe->regs_phys, | |
697 | REGS_SIZE, | |
698 | npe_name(npe)))) { | |
699 | print_npe(KERN_ERR, npe, | |
700 | "failed to request memory region\n"); | |
701 | continue; | |
702 | } | |
703 | ||
704 | if (npe_reset(npe)) | |
705 | continue; | |
706 | npe->valid = 1; | |
707 | found++; | |
708 | } | |
709 | ||
710 | if (!found) | |
3ba8c792 | 711 | return -ENODEV; |
82a96f57 KH |
712 | return 0; |
713 | } | |
714 | ||
715 | static void __exit npe_cleanup_module(void) | |
716 | { | |
717 | int i; | |
718 | ||
719 | for (i = 0; i < NPE_COUNT; i++) | |
720 | if (npe_tab[i].mem_res) { | |
721 | npe_reset(&npe_tab[i]); | |
722 | release_resource(npe_tab[i].mem_res); | |
723 | } | |
724 | } | |
725 | ||
726 | module_init(npe_init_module); | |
727 | module_exit(npe_cleanup_module); | |
728 | ||
729 | MODULE_AUTHOR("Krzysztof Halasa"); | |
730 | MODULE_LICENSE("GPL v2"); | |
05cd3db0 TG |
731 | MODULE_FIRMWARE(NPE_A_FIRMWARE); |
732 | MODULE_FIRMWARE(NPE_B_FIRMWARE); | |
733 | MODULE_FIRMWARE(NPE_C_FIRMWARE); | |
82a96f57 KH |
734 | |
735 | EXPORT_SYMBOL(npe_names); | |
736 | EXPORT_SYMBOL(npe_running); | |
737 | EXPORT_SYMBOL(npe_request); | |
738 | EXPORT_SYMBOL(npe_release); | |
739 | EXPORT_SYMBOL(npe_load_firmware); | |
740 | EXPORT_SYMBOL(npe_send_message); | |
741 | EXPORT_SYMBOL(npe_recv_message); | |
742 | EXPORT_SYMBOL(npe_send_recv_message); |