projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3145d8a6 RW |
1 | /* |
| 2 | * arch/arm/mach-ixp4xx/nas100d-pci.c | |
| 3 | * | |
| 4 | * NAS 100d board-level PCI initialization | |
| 5 | * | |
| 6 | * based on ixdp425-pci.c: | |
| 7 | * Copyright (C) 2002 Intel Corporation. | |
| 8 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
| 9 | * | |
| 10 | * Maintainer: http://www.nslu2-linux.org/ | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License version 2 as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | * | |
| 16 | */ | |
| 17 | ||
| 3145d8a6 RW |
18 | #include <linux/pci.h> |
| 19 | #include <linux/init.h> | |
| 698dfe2b | 20 | #include <linux/irq.h> |
| 3145d8a6 RW |
21 | #include <asm/mach/pci.h> |
| 22 | #include <asm/mach-types.h> | |
| 23 | ||
| 23fa6846 KH |
24 | #define NAS100D_PCI_MAX_DEV 3 |
| 25 | #define NAS100D_PCI_IRQ_LINES 3 | |
| 26 | ||
| 27 | /* PCI controller GPIO to IRQ pin mappings */ | |
| 28 | #define NAS100D_PCI_INTA_PIN 11 | |
| 29 | #define NAS100D_PCI_INTB_PIN 10 | |
| 30 | #define NAS100D_PCI_INTC_PIN 9 | |
| 31 | #define NAS100D_PCI_INTD_PIN 8 | |
| 32 | #define NAS100D_PCI_INTE_PIN 7 | |
| 33 | ||
| 34 | #define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 | |
| 35 | #define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 | |
| 36 | #define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 | |
| 37 | #define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 | |
| 38 | #define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 | |
| 39 | ||
| 3145d8a6 RW |
40 | void __init nas100d_pci_preinit(void) |
| 41 | { | |
| 6cab4860 DB |
42 | set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
| 43 | set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); | |
| 44 | set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | |
| 45 | set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | |
| 46 | set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); | |
| 3145d8a6 | 47 | |
| 3145d8a6 RW |
48 | ixp4xx_pci_preinit(); |
| 49 | } | |
| 50 | ||
| 51 | static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
| 52 | { | |
| 53 | static int pci_irq_table[NAS100D_PCI_MAX_DEV][NAS100D_PCI_IRQ_LINES] = | |
| 54 | { | |
| 55 | { IRQ_NAS100D_PCI_INTA, -1, -1 }, | |
| 56 | { IRQ_NAS100D_PCI_INTB, -1, -1 }, | |
| 57 | { IRQ_NAS100D_PCI_INTC, IRQ_NAS100D_PCI_INTD, IRQ_NAS100D_PCI_INTE }, | |
| 58 | }; | |
| 59 | ||
| 60 | int irq = -1; | |
| 61 | ||
| 62 | if (slot >= 1 && slot <= NAS100D_PCI_MAX_DEV && | |
| 63 | pin >= 1 && pin <= NAS100D_PCI_IRQ_LINES) | |
| 64 | irq = pci_irq_table[slot-1][pin-1]; | |
| 65 | ||
| 66 | return irq; | |
| 67 | } | |
| 68 | ||
| 69 | struct hw_pci __initdata nas100d_pci = { | |
| 70 | .nr_controllers = 1, | |
| 71 | .preinit = nas100d_pci_preinit, | |
| 72 | .swizzle = pci_std_swizzle, | |
| 73 | .setup = ixp4xx_setup, | |
| 74 | .scan = ixp4xx_scan_bus, | |
| 75 | .map_irq = nas100d_map_irq, | |
| 76 | }; | |
| 77 | ||
| 78 | int __init nas100d_pci_init(void) | |
| 79 | { | |
| 80 | if (machine_is_nas100d()) | |
| 81 | pci_common_init(&nas100d_pci); | |
| 82 | ||
| 83 | return 0; | |
| 84 | } | |
| 85 | ||
| 86 | subsys_initcall(nas100d_pci_init); |