[deliverable/linux.git] / arch / arm / mach-kirkwood / addr-map.c

/*
 * arch/arm/mach-kirkwood/addr-map.c
 *
 * Address map functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <plat/addr-map.h>
#include "common.h"

/*
 * Generic Address Decode Windows bit settings
 */
#define TARGET_DEV_BUS		1
#define TARGET_SRAM		3
#define TARGET_PCIE		4
#define ATTR_DEV_SPI_ROM	0x1e
#define ATTR_DEV_BOOT		0x1d
#define ATTR_DEV_NAND		0x2f
#define ATTR_DEV_CS3		0x37
#define ATTR_DEV_CS2		0x3b
#define ATTR_DEV_CS1		0x3d
#define ATTR_DEV_CS0		0x3e
#define ATTR_PCIE_IO		0xe0
#define ATTR_PCIE_MEM		0xe8
#define ATTR_PCIE1_IO		0xd0
#define ATTR_PCIE1_MEM		0xd8
#define ATTR_SRAM		0x01

/*
 * Description of the windows needed by the platform code
 */
static struct __initdata orion_addr_map_cfg addr_map_cfg = {
	.num_wins = 8,
	.remappable_wins = 4,
	.bridge_virt_base = BRIDGE_VIRT_BASE,
};

static const struct __initdata orion_addr_map_info addr_map_info[] = {
	/*
	 * Windows for PCIe IO+MEM space.
	 */
	{ 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
	  TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
	},
	{ 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
	  TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
	},
	{ 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
	  TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
	},
	{ 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
	  TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
	},
	/*
	 * Window for NAND controller.
	 */
	{ 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
	  TARGET_DEV_BUS, ATTR_DEV_NAND, -1
	},
	/*
	 * Window for SRAM.
	 */
	{ 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
	  TARGET_SRAM, ATTR_SRAM, -1
	},
	/* End marker */
	{ -1, 0, 0, 0, 0, 0 }
};

void __init kirkwood_setup_cpu_mbus(void)
{
	/*
	 * Disable, clear and configure windows.
	 */
	orion_config_wins(&addr_map_cfg, addr_map_info);

	/*
	 * Setup MBUS dram target info.
	 */
	orion_setup_cpu_mbus_target(&addr_map_cfg,
				    (void __iomem *) DDR_WINDOW_CPU_BASE);
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/addr-map.c
	3	*
	4	* Address map functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/mbus.h>
	14	#include <linux/io.h>
a09e64fb	15	#include <mach/hardware.h>
b6d1c33a	16	#include <plat/addr-map.h>
651c74c7 SB	17	#include "common.h"
	18
	19	/*
	20	* Generic Address Decode Windows bit settings
	21	*/
651c74c7	22	#define TARGET_DEV_BUS 1
c1191b0e	23	#define TARGET_SRAM 3
651c74c7 SB	24	#define TARGET_PCIE 4
	25	#define ATTR_DEV_SPI_ROM 0x1e
	26	#define ATTR_DEV_BOOT 0x1d
	27	#define ATTR_DEV_NAND 0x2f
	28	#define ATTR_DEV_CS3 0x37
	29	#define ATTR_DEV_CS2 0x3b
	30	#define ATTR_DEV_CS1 0x3d
	31	#define ATTR_DEV_CS0 0x3e
	32	#define ATTR_PCIE_IO 0xe0
	33	#define ATTR_PCIE_MEM 0xe8
ffd58bd2 SB	34	#define ATTR_PCIE1_IO 0xd0
ffd58bd2 SB	35	#define ATTR_PCIE1_MEM 0xd8
c1191b0e	36	#define ATTR_SRAM 0x01
651c74c7	37
651c74c7	38	/*
b6d1c33a	39	* Description of the windows needed by the platform code
651c74c7	40	*/
b6d1c33a AL	41	static struct __initdata orion_addr_map_cfg addr_map_cfg = {
	42	.num_wins = 8,
	43	.remappable_wins = 4,
9b7b7d8b	44	.bridge_virt_base = BRIDGE_VIRT_BASE,
b6d1c33a	45	};
651c74c7	46
b6d1c33a	47	static const struct __initdata orion_addr_map_info addr_map_info[] = {
651c74c7	48	/*
b6d1c33a	49	* Windows for PCIe IO+MEM space.
651c74c7	50	*/
b6d1c33a AL	51	{ 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
	52	TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
	53	},
	54	{ 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
	55	TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
	56	},
	57	{ 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
	58	TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
	59	},
	60	{ 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
	61	TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
	62	},
651c74c7	63	/*
b6d1c33a	64	* Window for NAND controller.
651c74c7	65	*/
b6d1c33a AL	66	{ 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
	67	TARGET_DEV_BUS, ATTR_DEV_NAND, -1
	68	},
651c74c7	69	/*
b6d1c33a	70	* Window for SRAM.
651c74c7	71	*/
b6d1c33a AL	72	{ 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
	73	TARGET_SRAM, ATTR_SRAM, -1
	74	},
	75	/* End marker */
	76	{ -1, 0, 0, 0, 0, 0 }
	77	};
651c74c7	78
b6d1c33a AL	79	void __init kirkwood_setup_cpu_mbus(void)
b6d1c33a AL	80	{
c1191b0e	81	/*
b6d1c33a	82	* Disable, clear and configure windows.
c1191b0e	83	*/
b6d1c33a	84	orion_config_wins(&addr_map_cfg, addr_map_info);
2d0c9e73	85
651c74c7 SB	86	/*
	87	* Setup MBUS dram target info.
	88	*/
9b7b7d8b TP	89	orion_setup_cpu_mbus_target(&addr_map_cfg,
9b7b7d8b TP	90	(void __iomem *) DDR_WINDOW_CPU_BASE);
651c74c7	91	}