Commit | Line | Data |
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651c74c7 SB |
1 | /* |
2 | * arch/arm/mach-kirkwood/common.c | |
3 | * | |
4 | * Core functions for Marvell Kirkwood SoCs | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/serial_8250.h> | |
15 | #include <linux/mbus.h> | |
651c74c7 | 16 | #include <linux/ata_platform.h> |
fb7b2d3f | 17 | #include <linux/mtd/nand.h> |
ee962723 | 18 | #include <linux/dma-mapping.h> |
dcf1cece | 19 | #include <net/dsa.h> |
651c74c7 SB |
20 | #include <asm/page.h> |
21 | #include <asm/timex.h> | |
9c15364f | 22 | #include <asm/kexec.h> |
651c74c7 SB |
23 | #include <asm/mach/map.h> |
24 | #include <asm/mach/time.h> | |
a09e64fb | 25 | #include <mach/kirkwood.h> |
fdd8b079 | 26 | #include <mach/bridge-regs.h> |
49106c72 | 27 | #include <plat/audio.h> |
6f088f1d | 28 | #include <plat/cache-feroceon-l2.h> |
8235ee00 | 29 | #include <plat/mvsdio.h> |
6f088f1d | 30 | #include <plat/orion_nand.h> |
28a2b450 | 31 | #include <plat/common.h> |
6f088f1d | 32 | #include <plat/time.h> |
651c74c7 SB |
33 | #include "common.h" |
34 | ||
35 | /***************************************************************************** | |
36 | * I/O Address Mapping | |
37 | ****************************************************************************/ | |
38 | static struct map_desc kirkwood_io_desc[] __initdata = { | |
39 | { | |
40 | .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, | |
41 | .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), | |
42 | .length = KIRKWOOD_PCIE_IO_SIZE, | |
43 | .type = MT_DEVICE, | |
ffd58bd2 SB |
44 | }, { |
45 | .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, | |
46 | .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), | |
47 | .length = KIRKWOOD_PCIE1_IO_SIZE, | |
48 | .type = MT_DEVICE, | |
651c74c7 SB |
49 | }, { |
50 | .virtual = KIRKWOOD_REGS_VIRT_BASE, | |
51 | .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), | |
52 | .length = KIRKWOOD_REGS_SIZE, | |
53 | .type = MT_DEVICE, | |
54 | }, | |
55 | }; | |
56 | ||
57 | void __init kirkwood_map_io(void) | |
58 | { | |
59 | iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); | |
60 | } | |
61 | ||
e8b2b7ba RK |
62 | /* |
63 | * Default clock control bits. Any bit _not_ set in this variable | |
64 | * will be cleared from the hardware after platform devices have been | |
65 | * registered. Some reserved bits must be set to 1. | |
66 | */ | |
67 | unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; | |
7e3819d8 | 68 | |
651c74c7 | 69 | |
651c74c7 SB |
70 | /***************************************************************************** |
71 | * EHCI0 | |
72 | ****************************************************************************/ | |
651c74c7 SB |
73 | void __init kirkwood_ehci_init(void) |
74 | { | |
e8b2b7ba | 75 | kirkwood_clk_ctrl |= CGC_USB0; |
4fcd3f37 AL |
76 | orion_ehci_init(&kirkwood_mbus_dram_info, |
77 | USB_PHYS_BASE, IRQ_KIRKWOOD_USB); | |
651c74c7 SB |
78 | } |
79 | ||
80 | ||
81 | /***************************************************************************** | |
82 | * GE00 | |
83 | ****************************************************************************/ | |
651c74c7 SB |
84 | void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
85 | { | |
e8b2b7ba | 86 | kirkwood_clk_ctrl |= CGC_GE0; |
651c74c7 | 87 | |
7e3819d8 AL |
88 | orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, |
89 | GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, | |
90 | IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); | |
651c74c7 SB |
91 | } |
92 | ||
93 | ||
d15fb9ef RS |
94 | /***************************************************************************** |
95 | * GE01 | |
96 | ****************************************************************************/ | |
d15fb9ef RS |
97 | void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) |
98 | { | |
7e3819d8 | 99 | |
e8b2b7ba | 100 | kirkwood_clk_ctrl |= CGC_GE1; |
d15fb9ef | 101 | |
7e3819d8 AL |
102 | orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, |
103 | GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, | |
104 | IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); | |
d15fb9ef RS |
105 | } |
106 | ||
107 | ||
dcf1cece LB |
108 | /***************************************************************************** |
109 | * Ethernet switch | |
110 | ****************************************************************************/ | |
dcf1cece LB |
111 | void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) |
112 | { | |
7e3819d8 | 113 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
114 | } |
115 | ||
116 | ||
fb7b2d3f NP |
117 | /***************************************************************************** |
118 | * NAND flash | |
119 | ****************************************************************************/ | |
120 | static struct resource kirkwood_nand_resource = { | |
121 | .flags = IORESOURCE_MEM, | |
122 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | |
123 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | |
124 | KIRKWOOD_NAND_MEM_SIZE - 1, | |
125 | }; | |
126 | ||
127 | static struct orion_nand_data kirkwood_nand_data = { | |
128 | .cle = 0, | |
129 | .ale = 1, | |
130 | .width = 8, | |
131 | }; | |
132 | ||
133 | static struct platform_device kirkwood_nand_flash = { | |
134 | .name = "orion_nand", | |
135 | .id = -1, | |
136 | .dev = { | |
137 | .platform_data = &kirkwood_nand_data, | |
138 | }, | |
139 | .resource = &kirkwood_nand_resource, | |
140 | .num_resources = 1, | |
141 | }; | |
142 | ||
143 | void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, | |
144 | int chip_delay) | |
145 | { | |
e8b2b7ba | 146 | kirkwood_clk_ctrl |= CGC_RUNIT; |
fb7b2d3f NP |
147 | kirkwood_nand_data.parts = parts; |
148 | kirkwood_nand_data.nr_parts = nr_parts; | |
149 | kirkwood_nand_data.chip_delay = chip_delay; | |
150 | platform_device_register(&kirkwood_nand_flash); | |
151 | } | |
152 | ||
010937ec BD |
153 | void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, |
154 | int (*dev_ready)(struct mtd_info *)) | |
155 | { | |
156 | kirkwood_clk_ctrl |= CGC_RUNIT; | |
157 | kirkwood_nand_data.parts = parts; | |
158 | kirkwood_nand_data.nr_parts = nr_parts; | |
159 | kirkwood_nand_data.dev_ready = dev_ready; | |
160 | platform_device_register(&kirkwood_nand_flash); | |
161 | } | |
fb7b2d3f | 162 | |
651c74c7 SB |
163 | /***************************************************************************** |
164 | * SoC RTC | |
165 | ****************************************************************************/ | |
5b99d534 | 166 | static void __init kirkwood_rtc_init(void) |
651c74c7 | 167 | { |
4748058c | 168 | orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); |
651c74c7 SB |
169 | } |
170 | ||
171 | ||
172 | /***************************************************************************** | |
173 | * SATA | |
174 | ****************************************************************************/ | |
651c74c7 SB |
175 | void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) |
176 | { | |
e8b2b7ba RK |
177 | kirkwood_clk_ctrl |= CGC_SATA0; |
178 | if (sata_data->n_ports > 1) | |
179 | kirkwood_clk_ctrl |= CGC_SATA1; | |
9e613f8a AL |
180 | |
181 | orion_sata_init(sata_data, &kirkwood_mbus_dram_info, | |
182 | SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); | |
651c74c7 SB |
183 | } |
184 | ||
185 | ||
8235ee00 NP |
186 | /***************************************************************************** |
187 | * SD/SDIO/MMC | |
188 | ****************************************************************************/ | |
189 | static struct resource mvsdio_resources[] = { | |
190 | [0] = { | |
191 | .start = SDIO_PHYS_BASE, | |
192 | .end = SDIO_PHYS_BASE + SZ_1K - 1, | |
193 | .flags = IORESOURCE_MEM, | |
194 | }, | |
195 | [1] = { | |
196 | .start = IRQ_KIRKWOOD_SDIO, | |
197 | .end = IRQ_KIRKWOOD_SDIO, | |
198 | .flags = IORESOURCE_IRQ, | |
199 | }, | |
200 | }; | |
201 | ||
5c602551 | 202 | static u64 mvsdio_dmamask = DMA_BIT_MASK(32); |
8235ee00 NP |
203 | |
204 | static struct platform_device kirkwood_sdio = { | |
205 | .name = "mvsdio", | |
206 | .id = -1, | |
207 | .dev = { | |
208 | .dma_mask = &mvsdio_dmamask, | |
5c602551 | 209 | .coherent_dma_mask = DMA_BIT_MASK(32), |
8235ee00 NP |
210 | }, |
211 | .num_resources = ARRAY_SIZE(mvsdio_resources), | |
212 | .resource = mvsdio_resources, | |
213 | }; | |
214 | ||
215 | void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) | |
216 | { | |
217 | u32 dev, rev; | |
218 | ||
219 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 220 | if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */ |
8235ee00 NP |
221 | mvsdio_data->clock = 100000000; |
222 | else | |
223 | mvsdio_data->clock = 200000000; | |
224 | mvsdio_data->dram = &kirkwood_mbus_dram_info; | |
e8b2b7ba | 225 | kirkwood_clk_ctrl |= CGC_SDIO; |
8235ee00 NP |
226 | kirkwood_sdio.dev.platform_data = mvsdio_data; |
227 | platform_device_register(&kirkwood_sdio); | |
228 | } | |
229 | ||
230 | ||
18365d18 LB |
231 | /***************************************************************************** |
232 | * SPI | |
233 | ****************************************************************************/ | |
18365d18 LB |
234 | void __init kirkwood_spi_init() |
235 | { | |
e8b2b7ba | 236 | kirkwood_clk_ctrl |= CGC_RUNIT; |
980f9f60 | 237 | orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk); |
18365d18 LB |
238 | } |
239 | ||
240 | ||
6574e001 MM |
241 | /***************************************************************************** |
242 | * I2C | |
243 | ****************************************************************************/ | |
6574e001 MM |
244 | void __init kirkwood_i2c_init(void) |
245 | { | |
aac7ffa3 | 246 | orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8); |
6574e001 MM |
247 | } |
248 | ||
249 | ||
651c74c7 SB |
250 | /***************************************************************************** |
251 | * UART0 | |
252 | ****************************************************************************/ | |
651c74c7 SB |
253 | |
254 | void __init kirkwood_uart0_init(void) | |
255 | { | |
28a2b450 AL |
256 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
257 | IRQ_KIRKWOOD_UART_0, kirkwood_tclk); | |
651c74c7 SB |
258 | } |
259 | ||
260 | ||
261 | /***************************************************************************** | |
262 | * UART1 | |
263 | ****************************************************************************/ | |
651c74c7 SB |
264 | void __init kirkwood_uart1_init(void) |
265 | { | |
28a2b450 AL |
266 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
267 | IRQ_KIRKWOOD_UART_1, kirkwood_tclk); | |
651c74c7 SB |
268 | } |
269 | ||
ae5c8c83 NP |
270 | /***************************************************************************** |
271 | * Cryptographic Engines and Security Accelerator (CESA) | |
272 | ****************************************************************************/ | |
273 | ||
274 | static struct resource kirkwood_crypto_res[] = { | |
275 | { | |
276 | .name = "regs", | |
277 | .start = CRYPTO_PHYS_BASE, | |
278 | .end = CRYPTO_PHYS_BASE + 0xffff, | |
279 | .flags = IORESOURCE_MEM, | |
280 | }, { | |
281 | .name = "sram", | |
282 | .start = KIRKWOOD_SRAM_PHYS_BASE, | |
283 | .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1, | |
284 | .flags = IORESOURCE_MEM, | |
285 | }, { | |
286 | .name = "crypto interrupt", | |
287 | .start = IRQ_KIRKWOOD_CRYPTO, | |
288 | .end = IRQ_KIRKWOOD_CRYPTO, | |
289 | .flags = IORESOURCE_IRQ, | |
290 | }, | |
291 | }; | |
292 | ||
293 | static struct platform_device kirkwood_crypto_device = { | |
294 | .name = "mv_crypto", | |
295 | .id = -1, | |
296 | .num_resources = ARRAY_SIZE(kirkwood_crypto_res), | |
297 | .resource = kirkwood_crypto_res, | |
298 | }; | |
299 | ||
300 | void __init kirkwood_crypto_init(void) | |
301 | { | |
302 | kirkwood_clk_ctrl |= CGC_CRYPTO; | |
303 | platform_device_register(&kirkwood_crypto_device); | |
304 | } | |
305 | ||
306 | ||
09c0ed2e SB |
307 | /***************************************************************************** |
308 | * XOR0 | |
309 | ****************************************************************************/ | |
5b99d534 | 310 | static void __init kirkwood_xor0_init(void) |
09c0ed2e | 311 | { |
e8b2b7ba | 312 | kirkwood_clk_ctrl |= CGC_XOR0; |
ee962723 AL |
313 | |
314 | orion_xor0_init(&kirkwood_mbus_dram_info, | |
315 | XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, | |
316 | IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); | |
09c0ed2e SB |
317 | } |
318 | ||
319 | ||
320 | /***************************************************************************** | |
321 | * XOR1 | |
322 | ****************************************************************************/ | |
5b99d534 | 323 | static void __init kirkwood_xor1_init(void) |
09c0ed2e | 324 | { |
e8b2b7ba | 325 | kirkwood_clk_ctrl |= CGC_XOR1; |
ee962723 AL |
326 | |
327 | orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, | |
328 | IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); | |
09c0ed2e SB |
329 | } |
330 | ||
331 | ||
054bd3f0 TR |
332 | /***************************************************************************** |
333 | * Watchdog | |
334 | ****************************************************************************/ | |
054bd3f0 TR |
335 | static void __init kirkwood_wdt_init(void) |
336 | { | |
5e00d378 | 337 | orion_wdt_init(kirkwood_tclk); |
054bd3f0 TR |
338 | } |
339 | ||
340 | ||
651c74c7 SB |
341 | /***************************************************************************** |
342 | * Time handling | |
343 | ****************************************************************************/ | |
4ee1f6b5 LB |
344 | void __init kirkwood_init_early(void) |
345 | { | |
346 | orion_time_set_base(TIMER_VIRT_BASE); | |
347 | } | |
348 | ||
79d4dd77 RS |
349 | int kirkwood_tclk; |
350 | ||
9b8ebfec | 351 | static int __init kirkwood_find_tclk(void) |
79d4dd77 | 352 | { |
b2b3dc2f RS |
353 | u32 dev, rev; |
354 | ||
355 | kirkwood_pcie_id(&dev, &rev); | |
1e4d2d3d | 356 | |
2fa0f939 SG |
357 | if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID) |
358 | if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0) | |
359 | return 200000000; | |
b2b3dc2f | 360 | |
79d4dd77 RS |
361 | return 166666667; |
362 | } | |
363 | ||
6de95c19 | 364 | static void __init kirkwood_timer_init(void) |
651c74c7 | 365 | { |
79d4dd77 | 366 | kirkwood_tclk = kirkwood_find_tclk(); |
4ee1f6b5 LB |
367 | |
368 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
369 | IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); | |
651c74c7 SB |
370 | } |
371 | ||
372 | struct sys_timer kirkwood_timer = { | |
373 | .init = kirkwood_timer_init, | |
374 | }; | |
375 | ||
49106c72 | 376 | /***************************************************************************** |
377 | * Audio | |
378 | ****************************************************************************/ | |
379 | static struct resource kirkwood_i2s_resources[] = { | |
380 | [0] = { | |
381 | .start = AUDIO_PHYS_BASE, | |
382 | .end = AUDIO_PHYS_BASE + SZ_16K - 1, | |
383 | .flags = IORESOURCE_MEM, | |
384 | }, | |
385 | [1] = { | |
386 | .start = IRQ_KIRKWOOD_I2S, | |
387 | .end = IRQ_KIRKWOOD_I2S, | |
388 | .flags = IORESOURCE_IRQ, | |
389 | }, | |
390 | }; | |
391 | ||
392 | static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { | |
393 | .dram = &kirkwood_mbus_dram_info, | |
394 | .burst = 128, | |
395 | }; | |
396 | ||
397 | static struct platform_device kirkwood_i2s_device = { | |
398 | .name = "kirkwood-i2s", | |
399 | .id = -1, | |
400 | .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), | |
401 | .resource = kirkwood_i2s_resources, | |
402 | .dev = { | |
403 | .platform_data = &kirkwood_i2s_data, | |
404 | }, | |
405 | }; | |
406 | ||
f0fba2ad | 407 | static struct platform_device kirkwood_pcm_device = { |
c88e7b93 | 408 | .name = "kirkwood-pcm-audio", |
f0fba2ad LG |
409 | .id = -1, |
410 | }; | |
411 | ||
49106c72 | 412 | void __init kirkwood_audio_init(void) |
413 | { | |
414 | kirkwood_clk_ctrl |= CGC_AUDIO; | |
415 | platform_device_register(&kirkwood_i2s_device); | |
f0fba2ad | 416 | platform_device_register(&kirkwood_pcm_device); |
49106c72 | 417 | } |
651c74c7 SB |
418 | |
419 | /***************************************************************************** | |
420 | * General | |
421 | ****************************************************************************/ | |
b2b3dc2f RS |
422 | /* |
423 | * Identify device ID and revision. | |
424 | */ | |
651c74c7 SB |
425 | static char * __init kirkwood_id(void) |
426 | { | |
b2b3dc2f RS |
427 | u32 dev, rev; |
428 | ||
429 | kirkwood_pcie_id(&dev, &rev); | |
430 | ||
431 | if (dev == MV88F6281_DEV_ID) { | |
432 | if (rev == MV88F6281_REV_Z0) | |
433 | return "MV88F6281-Z0"; | |
434 | else if (rev == MV88F6281_REV_A0) | |
435 | return "MV88F6281-A0"; | |
aec1bad3 SG |
436 | else if (rev == MV88F6281_REV_A1) |
437 | return "MV88F6281-A1"; | |
b2b3dc2f RS |
438 | else |
439 | return "MV88F6281-Rev-Unsupported"; | |
440 | } else if (dev == MV88F6192_DEV_ID) { | |
441 | if (rev == MV88F6192_REV_Z0) | |
442 | return "MV88F6192-Z0"; | |
443 | else if (rev == MV88F6192_REV_A0) | |
444 | return "MV88F6192-A0"; | |
1c2003a1 SB |
445 | else if (rev == MV88F6192_REV_A1) |
446 | return "MV88F6192-A1"; | |
b2b3dc2f RS |
447 | else |
448 | return "MV88F6192-Rev-Unsupported"; | |
449 | } else if (dev == MV88F6180_DEV_ID) { | |
450 | if (rev == MV88F6180_REV_A0) | |
451 | return "MV88F6180-Rev-A0"; | |
1c2003a1 SB |
452 | else if (rev == MV88F6180_REV_A1) |
453 | return "MV88F6180-Rev-A1"; | |
b2b3dc2f RS |
454 | else |
455 | return "MV88F6180-Rev-Unsupported"; | |
1e4d2d3d SB |
456 | } else if (dev == MV88F6282_DEV_ID) { |
457 | if (rev == MV88F6282_REV_A0) | |
458 | return "MV88F6282-Rev-A0"; | |
459 | else | |
460 | return "MV88F6282-Rev-Unsupported"; | |
b2b3dc2f RS |
461 | } else { |
462 | return "Device-Unknown"; | |
651c74c7 | 463 | } |
651c74c7 SB |
464 | } |
465 | ||
4360bb41 | 466 | static void __init kirkwood_l2_init(void) |
13387603 | 467 | { |
4360bb41 RS |
468 | #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH |
469 | writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); | |
470 | feroceon_l2_init(1); | |
471 | #else | |
472 | writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG); | |
473 | feroceon_l2_init(0); | |
474 | #endif | |
13387603 SB |
475 | } |
476 | ||
651c74c7 SB |
477 | void __init kirkwood_init(void) |
478 | { | |
479 | printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", | |
79d4dd77 | 480 | kirkwood_id(), kirkwood_tclk); |
49106c72 | 481 | kirkwood_i2s_data.tclk = kirkwood_tclk; |
651c74c7 | 482 | |
2bf30108 LB |
483 | /* |
484 | * Disable propagation of mbus errors to the CPU local bus, | |
485 | * as this causes mbus errors (which can occur for example | |
486 | * for PCI aborts) to throw CPU aborts, which we're not set | |
487 | * up to deal with. | |
488 | */ | |
489 | writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); | |
490 | ||
651c74c7 SB |
491 | kirkwood_setup_cpu_mbus(); |
492 | ||
493 | #ifdef CONFIG_CACHE_FEROCEON_L2 | |
4360bb41 | 494 | kirkwood_l2_init(); |
651c74c7 | 495 | #endif |
5b99d534 NP |
496 | |
497 | /* internal devices that every board has */ | |
498 | kirkwood_rtc_init(); | |
054bd3f0 | 499 | kirkwood_wdt_init(); |
5b99d534 NP |
500 | kirkwood_xor0_init(); |
501 | kirkwood_xor1_init(); | |
ae5c8c83 | 502 | kirkwood_crypto_init(); |
9c15364f EC |
503 | |
504 | #ifdef CONFIG_KEXEC | |
505 | kexec_reinit = kirkwood_enable_pcie; | |
506 | #endif | |
651c74c7 | 507 | } |
e8b2b7ba RK |
508 | |
509 | static int __init kirkwood_clock_gate(void) | |
510 | { | |
511 | unsigned int curr = readl(CLOCK_GATING_CTRL); | |
ffd58bd2 | 512 | u32 dev, rev; |
e8b2b7ba | 513 | |
ffd58bd2 | 514 | kirkwood_pcie_id(&dev, &rev); |
e8b2b7ba RK |
515 | printk(KERN_DEBUG "Gating clock of unused units\n"); |
516 | printk(KERN_DEBUG "before: 0x%08x\n", curr); | |
517 | ||
518 | /* Make sure those units are accessible */ | |
ffd58bd2 | 519 | writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL); |
e8b2b7ba RK |
520 | |
521 | /* For SATA: first shutdown the phy */ | |
522 | if (!(kirkwood_clk_ctrl & CGC_SATA0)) { | |
523 | /* Disable PLL and IVREF */ | |
524 | writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2); | |
525 | /* Disable PHY */ | |
526 | writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL); | |
527 | } | |
528 | if (!(kirkwood_clk_ctrl & CGC_SATA1)) { | |
529 | /* Disable PLL and IVREF */ | |
530 | writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2); | |
531 | /* Disable PHY */ | |
532 | writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL); | |
533 | } | |
534 | ||
535 | /* For PCIe: first shutdown the phy */ | |
536 | if (!(kirkwood_clk_ctrl & CGC_PEX0)) { | |
537 | writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL); | |
538 | while (1) | |
539 | if (readl(PCIE_STATUS) & 0x1) | |
540 | break; | |
541 | writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL); | |
542 | } | |
543 | ||
ffd58bd2 SB |
544 | /* For PCIe 1: first shutdown the phy */ |
545 | if (dev == MV88F6282_DEV_ID) { | |
546 | if (!(kirkwood_clk_ctrl & CGC_PEX1)) { | |
547 | writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL); | |
548 | while (1) | |
549 | if (readl(PCIE1_STATUS) & 0x1) | |
550 | break; | |
551 | writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL); | |
552 | } | |
553 | } else /* keep this bit set for devices that don't have PCIe1 */ | |
554 | kirkwood_clk_ctrl |= CGC_PEX1; | |
555 | ||
e8b2b7ba RK |
556 | /* Now gate clock the required units */ |
557 | writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL); | |
558 | printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL)); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | late_initcall(kirkwood_clock_gate); |