[deliverable/linux.git] / arch / arm / mach-kirkwood / pcie.c

/*
 * arch/arm/mach-kirkwood/pcie.c
 *
 * PCIe functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
#include <plat/addr-map.h>
#include "common.h"

static void kirkwood_enable_pcie_clk(const char *port)
{
	struct clk *clk;

	clk = clk_get_sys("pcie", port);
	if (IS_ERR(clk)) {
		pr_err("PCIE clock %s missing\n", port);
		return;
	}
	clk_prepare_enable(clk);
	clk_put(clk);
}

/* This function is called very early in the boot when probing the
   hardware to determine what we actually are, and what rate tclk is
   ticking at. Hence calling kirkwood_enable_pcie_clk() is not
   possible since the clk tree has not been created yet. */
void kirkwood_enable_pcie(void)
{
	u32 curr = readl(CLOCK_GATING_CTRL);
	if (!(curr & CGC_PEX0))
		writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
}

void kirkwood_pcie_id(u32 *dev, u32 *rev)
{
	kirkwood_enable_pcie();
	*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
	*rev = orion_pcie_rev(PCIE_VIRT_BASE);
}

struct pcie_port {
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	int			irq;
	struct resource		res;
};

static int pcie_port_map[2];
static int num_pcie_ports;

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == pp->root_bus_nr && dev == 0)
		return 1;

	if (!orion_pcie_link_up(pp->base))
		return 0;

	if (bus == pp->root_bus_nr && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static void __init pcie0_ioresources_init(struct pcie_port *pp)
{
	pp->base = PCIE_VIRT_BASE;
	pp->irq	= IRQ_KIRKWOOD_PCIE;

	/*
	 * IORESOURCE_MEM
	 */
	pp->res.name = "PCIe 0 MEM";
	pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	pp->res.flags = IORESOURCE_MEM;
}

static void __init pcie1_ioresources_init(struct pcie_port *pp)
{
	pp->base = PCIE1_VIRT_BASE;
	pp->irq	= IRQ_KIRKWOOD_PCIE1;

	/*
	 * IORESOURCE_MEM
	 */
	pp->res.name = "PCIe 1 MEM";
	pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	pp->res.flags = IORESOURCE_MEM;
}

static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct pcie_port *pp;
	int index;

	if (nr >= num_pcie_ports)
		return 0;

	index = pcie_port_map[nr];
	pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);

	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	if (!pp)
		panic("PCIe: failed to allocate pcie_port data");
	sys->private_data = pp;
	pp->root_bus_nr = sys->busnr;
	spin_lock_init(&pp->conf_lock);

	switch (index) {
	case 0:
		kirkwood_enable_pcie_clk("0");
		pcie0_ioresources_init(pp);
		pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
		break;
	case 1:
		kirkwood_enable_pcie_clk("1");
		pcie1_ioresources_init(pp);
		pci_ioremap_io(SZ_64K * sys->busnr,
			       KIRKWOOD_PCIE1_IO_PHYS_BASE);
		break;
	default:
		panic("PCIe setup: invalid controller %d", index);
	}

	if (request_resource(&iomem_resource, &pp->res))
		panic("Request PCIe%d Memory resource failed\n", index);

	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base);

	return 1;
}

/*
 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
 * is operating as a root complex this needs to be switched to
 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
 * the device. Decoding setup is handled by the orion code.
 */
static void rc_pci_fixup(struct pci_dev *dev)
{
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		dev->class &= 0xff;
		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
	u8 pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	struct pcie_port *pp = sys->private_data;

	return pp->irq;
}

static struct hw_pci kirkwood_pci __initdata = {
	.setup		= kirkwood_pcie_setup,
	.map_irq	= kirkwood_pcie_map_irq,
	.ops            = &pcie_ops,
};

static void __init add_pcie_port(int index, void __iomem *base)
{
	pcie_port_map[num_pcie_ports++] = index;
	pr_info("Kirkwood PCIe port %d: link %s\n", index,
		orion_pcie_link_up(base) ? "up" : "down");
}

void __init kirkwood_pcie_init(unsigned int portmask)
{
	vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;

	if (portmask & KW_PCIE0)
		add_pcie_port(0, PCIE_VIRT_BASE);

	if (portmask & KW_PCIE1)
		add_pcie_port(1, PCIE1_VIRT_BASE);

	kirkwood_pci.nr_controllers = num_pcie_ports;
	pci_common_init(&kirkwood_pci);
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/pcie.c
	3	*
	4	* PCIe functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
5a0e3ad6	13	#include <linux/slab.h>
27e53cfb	14	#include <linux/clk.h>
cc22b4c1	15	#include <video/vga.h>
6e5c11a1	16	#include <asm/irq.h>
651c74c7	17	#include <asm/mach/pci.h>
6f088f1d	18	#include <plat/pcie.h>
e8b2b7ba	19	#include <mach/bridge-regs.h>
45173d5e	20	#include <plat/addr-map.h>
651c74c7 SB	21	#include "common.h"
651c74c7 SB	22
27e53cfb AL	23	static void kirkwood_enable_pcie_clk(const char *port)
	24	{
	25	struct clk *clk;
	26
	27	clk = clk_get_sys("pcie", port);
	28	if (IS_ERR(clk)) {
98adf932	29	pr_err("PCIE clock %s missing\n", port);
27e53cfb AL	30	return;
	31	}
	32	clk_prepare_enable(clk);
	33	clk_put(clk);
	34	}
	35
	36	/* This function is called very early in the boot when probing the
	37	hardware to determine what we actually are, and what rate tclk is
	38	ticking at. Hence calling kirkwood_enable_pcie_clk() is not
	39	possible since the clk tree has not been created yet. */
0e0cdd37 EC	40	void kirkwood_enable_pcie(void)
	41	{
	42	u32 curr = readl(CLOCK_GATING_CTRL);
	43	if (!(curr & CGC_PEX0))
	44	writel(curr \| CGC_PEX0, CLOCK_GATING_CTRL);
	45	}
	46
98d9986c	47	void kirkwood_pcie_id(u32 dev, u32 rev)
ffd58bd2	48	{
0e0cdd37	49	kirkwood_enable_pcie();
060f3d19 TP	50	*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
060f3d19 TP	51	*rev = orion_pcie_rev(PCIE_VIRT_BASE);
ffd58bd2	52	}
651c74c7	53
ffd58bd2 SB	54	struct pcie_port {
	55	u8 root_bus_nr;
	56	void __iomem *base;
	57	spinlock_t conf_lock;
	58	int irq;
2bb08085	59	struct resource res;
ffd58bd2	60	};
651c74c7	61
ffd58bd2 SB	62	static int pcie_port_map[2];
	63	static int num_pcie_ports;
	64
ffd58bd2	65	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
651c74c7 SB	66	{
	67	/*
	68	* Don't go out when trying to access --
	69	* 1. nonexisting device on local bus
	70	* 2. where there's no device connected (no link)
	71	*/
ffd58bd2	72	if (bus == pp->root_bus_nr && dev == 0)
651c74c7 SB	73	return 1;
651c74c7 SB	74
ffd58bd2	75	if (!orion_pcie_link_up(pp->base))
651c74c7 SB	76	return 0;
651c74c7 SB	77
ffd58bd2	78	if (bus == pp->root_bus_nr && dev != 1)
651c74c7 SB	79	return 0;
	80
	81	return 1;
	82	}
	83
	84
	85	/*
	86	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
	87	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	88	* transactions are atomic.
	89	*/
651c74c7 SB	90
	91	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	92	int size, u32 *val)
	93	{
43ba990b RK	94	struct pci_sys_data *sys = bus->sysdata;
43ba990b RK	95	struct pcie_port *pp = sys->private_data;
651c74c7 SB	96	unsigned long flags;
	97	int ret;
	98
ffd58bd2	99	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
651c74c7 SB	100	*val = 0xffffffff;
	101	return PCIBIOS_DEVICE_NOT_FOUND;
	102	}
	103
ffd58bd2 SB	104	spin_lock_irqsave(&pp->conf_lock, flags);
	105	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	106	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	107
	108	return ret;
	109	}
	110
	111	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
	112	int where, int size, u32 val)
	113	{
43ba990b RK	114	struct pci_sys_data *sys = bus->sysdata;
43ba990b RK	115	struct pcie_port *pp = sys->private_data;
651c74c7 SB	116	unsigned long flags;
	117	int ret;
	118
ffd58bd2	119	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
651c74c7 SB	120	return PCIBIOS_DEVICE_NOT_FOUND;
651c74c7 SB	121
ffd58bd2 SB	122	spin_lock_irqsave(&pp->conf_lock, flags);
	123	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	124	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	125
	126	return ret;
	127	}
	128
	129	static struct pci_ops pcie_ops = {
	130	.read = pcie_rd_conf,
	131	.write = pcie_wr_conf,
	132	};
	133
a87182b3	134	static void __init pcie0_ioresources_init(struct pcie_port *pp)
651c74c7	135	{
060f3d19	136	pp->base = PCIE_VIRT_BASE;
a87182b3	137	pp->irq = IRQ_KIRKWOOD_PCIE;
651c74c7	138
651c74c7	139	/*
ffd58bd2	140	* IORESOURCE_MEM
651c74c7	141	*/
2bb08085 RH	142	pp->res.name = "PCIe 0 MEM";
	143	pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	144	pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	145	pp->res.flags = IORESOURCE_MEM;
ffd58bd2 SB	146	}
ffd58bd2 SB	147
a87182b3	148	static void __init pcie1_ioresources_init(struct pcie_port *pp)
ffd58bd2	149	{
060f3d19	150	pp->base = PCIE1_VIRT_BASE;
a87182b3	151	pp->irq = IRQ_KIRKWOOD_PCIE1;
651c74c7	152
651c74c7 SB	153	/*
	154	* IORESOURCE_MEM
	155	*/
2bb08085 RH	156	pp->res.name = "PCIe 1 MEM";
	157	pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	158	pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	159	pp->res.flags = IORESOURCE_MEM;
ffd58bd2 SB	160	}
	161
	162	static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
	163	{
ffd58bd2 SB	164	struct pcie_port *pp;
	165	int index;
	166
	167	if (nr >= num_pcie_ports)
	168	return 0;
	169
	170	index = pcie_port_map[nr];
98adf932	171	pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
ffd58bd2 SB	172
	173	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	174	if (!pp)
	175	panic("PCIe: failed to allocate pcie_port data");
	176	sys->private_data = pp;
	177	pp->root_bus_nr = sys->busnr;
	178	spin_lock_init(&pp->conf_lock);
	179
	180	switch (index) {
	181	case 0:
27e53cfb	182	kirkwood_enable_pcie_clk("0");
a87182b3	183	pcie0_ioresources_init(pp);
2bb08085	184	pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
ffd58bd2 SB	185	break;
ffd58bd2 SB	186	case 1:
27e53cfb	187	kirkwood_enable_pcie_clk("1");
a87182b3	188	pcie1_ioresources_init(pp);
98adf932 AL	189	pci_ioremap_io(SZ_64K * sys->busnr,
98adf932 AL	190	KIRKWOOD_PCIE1_IO_PHYS_BASE);
ffd58bd2 SB	191	break;
ffd58bd2 SB	192	default:
a87182b3	193	panic("PCIe setup: invalid controller %d", index);
ffd58bd2 SB	194	}
ffd58bd2 SB	195
2bb08085	196	if (request_resource(&iomem_resource, &pp->res))
a87182b3 NP	197	panic("Request PCIe%d Memory resource failed\n", index);
a87182b3 NP	198
2bb08085	199	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
a87182b3	200
ffd58bd2 SB	201	/*
	202	* Generic PCIe unit setup.
	203	*/
	204	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	205
63a9332b	206	orion_pcie_setup(pp->base);
e8b2b7ba	207
651c74c7 SB	208	return 1;
	209	}
	210
1dc831bf JG	211	/*
	212	* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
	213	* is operating as a root complex this needs to be switched to
	214	* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
	215	* the device. Decoding setup is handled by the orion code.
	216	*/
351a102d	217	static void rc_pci_fixup(struct pci_dev *dev)
651c74c7	218	{
651c74c7 SB	219	if (dev->bus->parent == NULL && dev->devfn == 0) {
	220	int i;
	221
1dc831bf JG	222	dev->class &= 0xff;
1dc831bf JG	223	dev->class \|= PCI_CLASS_BRIDGE_HOST << 8;
651c74c7 SB	224	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	225	dev->resource[i].start = 0;
	226	dev->resource[i].end = 0;
	227	dev->resource[i].flags = 0;
	228	}
	229	}
	230	}
	231	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	232
d5341942 RB	233	static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
d5341942 RB	234	u8 pin)
651c74c7	235	{
43ba990b RK	236	struct pci_sys_data *sys = dev->sysdata;
43ba990b RK	237	struct pcie_port *pp = sys->private_data;
ffd58bd2 SB	238
ffd58bd2 SB	239	return pp->irq;
651c74c7 SB	240	}
	241
	242	static struct hw_pci kirkwood_pci __initdata = {
651c74c7	243	.setup = kirkwood_pcie_setup,
651c74c7	244	.map_irq = kirkwood_pcie_map_irq,
4a9329a0	245	.ops = &pcie_ops,
651c74c7 SB	246	};
651c74c7 SB	247
060f3d19	248	static void __init add_pcie_port(int index, void __iomem *base)
ffd58bd2	249	{
b73690c8 JG	250	pcie_port_map[num_pcie_ports++] = index;
	251	pr_info("Kirkwood PCIe port %d: link %s\n", index,
	252	orion_pcie_link_up(base) ? "up" : "down");
ffd58bd2 SB	253	}
	254
	255	void __init kirkwood_pcie_init(unsigned int portmask)
651c74c7	256	{
cc22b4c1 RH	257	vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
cc22b4c1 RH	258
ffd58bd2 SB	259	if (portmask & KW_PCIE0)
	260	add_pcie_port(0, PCIE_VIRT_BASE);
	261
	262	if (portmask & KW_PCIE1)
	263	add_pcie_port(1, PCIE1_VIRT_BASE);
	264
	265	kirkwood_pci.nr_controllers = num_pcie_ports;
651c74c7 SB	266	pci_common_init(&kirkwood_pci);
651c74c7 SB	267	}