[deliverable/linux.git] / arch / arm / mach-kirkwood / pcie.c

/*
 * arch/arm/mach-kirkwood/pcie.c
 *
 * PCIe functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
#include "common.h"

void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
}

struct pcie_port {
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	int			irq;
	struct resource		res[2];
};

static int pcie_port_map[2];
static int num_pcie_ports;

static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
{
	struct pci_sys_data *sys = bus->sysdata;
	return sys->private_data;
}

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == pp->root_bus_nr && dev == 0)
		return 1;

	if (!orion_pcie_link_up(pp->base))
		return 0;

	if (bus == pp->root_bus_nr && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pcie_port *pp = bus_to_port(bus);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pcie_port *pp = bus_to_port(bus);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static int __init pcie0_ioresources_setup(struct pci_sys_data *sys)
{
	struct pcie_port *pp = (struct pcie_port *)sys->private_data;

	/*
	 * IORESOURCE_IO
	 */
	pp->res[0].name = "PCIe 0 I/O Space";
	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
	pp->res[0].flags = IORESOURCE_IO;
	if (request_resource(&ioport_resource, &pp->res[0]))
		panic("Request PCIe 0 IO resource failed\n");
	sys->resource[0] = &pp->res[0];

	/*
	 * IORESOURCE_MEM
	 */
	pp->res[1].name = "PCIe 0 MEM";
	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	pp->res[1].flags = IORESOURCE_MEM;
	if (request_resource(&iomem_resource, &pp->res[1]))
		panic("Request PCIe 0 Memory resource failed\n");
	sys->resource[1] = &pp->res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

static int __init pcie1_ioresources_setup(struct pci_sys_data *sys)
{
	struct pcie_port *pp = (struct pcie_port *)sys->private_data;

	/*
	 * IORESOURCE_IO
	 */
	pp->res[0].name = "PCIe 1 I/O Space";
	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
	pp->res[0].flags = IORESOURCE_IO;
	if (request_resource(&ioport_resource, &pp->res[0]))
		panic("Request PCIe 1 IO resource failed\n");
	sys->resource[0] = &pp->res[0];

	/*
	 * IORESOURCE_MEM
	 */
	pp->res[1].name = "PCIe 1 MEM";
	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	pp->res[1].flags = IORESOURCE_MEM;
	if (request_resource(&iomem_resource, &pp->res[1]))
		panic("Request PCIe 1 Memory resource failed\n");
	sys->resource[1] = &pp->res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
{
	extern unsigned int kirkwood_clk_ctrl;
	struct pcie_port *pp;
	int index;

	if (nr >= num_pcie_ports)
		return 0;

	index = pcie_port_map[nr];
	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);

	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	if (!pp)
		panic("PCIe: failed to allocate pcie_port data");
	sys->private_data = pp;
	pp->root_bus_nr = sys->busnr;
	spin_lock_init(&pp->conf_lock);

	switch (index) {
	case 0:
		pp->base = (void __iomem *)PCIE_VIRT_BASE;
		pp->irq	= IRQ_KIRKWOOD_PCIE;
		kirkwood_clk_ctrl |= CGC_PEX0;
		pcie0_ioresources_setup(sys);
		break;
	case 1:
		pp->base = (void __iomem *)PCIE1_VIRT_BASE;
		pp->irq	= IRQ_KIRKWOOD_PCIE1;
		kirkwood_clk_ctrl |= CGC_PEX1;
		pcie1_ioresources_setup(sys);
		break;
	default:
		panic("PCIe setup: invalid controller");
	}

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);

	return 1;
}

static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static struct pci_bus __init *
kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr < num_pcie_ports) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pcie_port *pp = bus_to_port(dev->bus);

	return pp->irq;
}

static struct hw_pci kirkwood_pci __initdata = {
	.swizzle	= pci_std_swizzle,
	.setup		= kirkwood_pcie_setup,
	.scan		= kirkwood_pcie_scan_bus,
	.map_irq	= kirkwood_pcie_map_irq,
};

static void __init add_pcie_port(int index, unsigned long base)
{
	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);

	if (orion_pcie_link_up((void __iomem *)base)) {
		printk(KERN_INFO "link up\n");
		pcie_port_map[num_pcie_ports++] = index;
	} else
		printk(KERN_INFO "link down, ignoring\n");
}

void __init kirkwood_pcie_init(unsigned int portmask)
{
	if (portmask & KW_PCIE0)
		add_pcie_port(0, PCIE_VIRT_BASE);

	if (portmask & KW_PCIE1)
		add_pcie_port(1, PCIE1_VIRT_BASE);

	kirkwood_pci.nr_controllers = num_pcie_ports;
	pci_common_init(&kirkwood_pci);
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/pcie.c
	3	*
	4	* PCIe functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
5a0e3ad6	13	#include <linux/slab.h>
651c74c7	14	#include <linux/mbus.h>
6e5c11a1	15	#include <asm/irq.h>
651c74c7	16	#include <asm/mach/pci.h>
6f088f1d	17	#include <plat/pcie.h>
e8b2b7ba	18	#include <mach/bridge-regs.h>
651c74c7 SB	19	#include "common.h"
651c74c7 SB	20
ffd58bd2 SB	21	void __init kirkwood_pcie_id(u32 dev, u32 rev)
	22	{
	23	dev = orion_pcie_dev_id((void __iomem )PCIE_VIRT_BASE);
	24	rev = orion_pcie_rev((void __iomem )PCIE_VIRT_BASE);
	25	}
651c74c7	26
ffd58bd2 SB	27	struct pcie_port {
	28	u8 root_bus_nr;
	29	void __iomem *base;
	30	spinlock_t conf_lock;
	31	int irq;
	32	struct resource res[2];
	33	};
651c74c7	34
ffd58bd2 SB	35	static int pcie_port_map[2];
	36	static int num_pcie_ports;
	37
	38	static inline struct pcie_port bus_to_port(struct pci_bus bus)
b2b3dc2f	39	{
ffd58bd2 SB	40	struct pci_sys_data *sys = bus->sysdata;
ffd58bd2 SB	41	return sys->private_data;
b2b3dc2f RS	42	}
b2b3dc2f RS	43
ffd58bd2	44	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
651c74c7 SB	45	{
	46	/*
	47	* Don't go out when trying to access --
	48	* 1. nonexisting device on local bus
	49	* 2. where there's no device connected (no link)
	50	*/
ffd58bd2	51	if (bus == pp->root_bus_nr && dev == 0)
651c74c7 SB	52	return 1;
651c74c7 SB	53
ffd58bd2	54	if (!orion_pcie_link_up(pp->base))
651c74c7 SB	55	return 0;
651c74c7 SB	56
ffd58bd2	57	if (bus == pp->root_bus_nr && dev != 1)
651c74c7 SB	58	return 0;
	59
	60	return 1;
	61	}
	62
	63
	64	/*
	65	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
	66	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	67	* transactions are atomic.
	68	*/
651c74c7 SB	69
	70	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	71	int size, u32 *val)
	72	{
ffd58bd2	73	struct pcie_port *pp = bus_to_port(bus);
651c74c7 SB	74	unsigned long flags;
	75	int ret;
	76
ffd58bd2	77	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
651c74c7 SB	78	*val = 0xffffffff;
	79	return PCIBIOS_DEVICE_NOT_FOUND;
	80	}
	81
ffd58bd2 SB	82	spin_lock_irqsave(&pp->conf_lock, flags);
	83	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	84	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	85
	86	return ret;
	87	}
	88
	89	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
	90	int where, int size, u32 val)
	91	{
ffd58bd2	92	struct pcie_port *pp = bus_to_port(bus);
651c74c7 SB	93	unsigned long flags;
	94	int ret;
	95
ffd58bd2	96	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
651c74c7 SB	97	return PCIBIOS_DEVICE_NOT_FOUND;
651c74c7 SB	98
ffd58bd2 SB	99	spin_lock_irqsave(&pp->conf_lock, flags);
	100	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	101	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	102
	103	return ret;
	104	}
	105
	106	static struct pci_ops pcie_ops = {
	107	.read = pcie_rd_conf,
	108	.write = pcie_wr_conf,
	109	};
	110
ffd58bd2	111	static int __init pcie0_ioresources_setup(struct pci_sys_data *sys)
651c74c7	112	{
ffd58bd2	113	struct pcie_port pp = (struct pcie_port )sys->private_data;
651c74c7 SB	114
651c74c7 SB	115	/*
ffd58bd2	116	* IORESOURCE_IO
651c74c7	117	*/
ffd58bd2 SB	118	pp->res[0].name = "PCIe 0 I/O Space";
	119	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
	120	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
	121	pp->res[0].flags = IORESOURCE_IO;
	122	if (request_resource(&ioport_resource, &pp->res[0]))
	123	panic("Request PCIe 0 IO resource failed\n");
	124	sys->resource[0] = &pp->res[0];
651c74c7 SB	125
651c74c7 SB	126	/*
ffd58bd2	127	* IORESOURCE_MEM
651c74c7	128	*/
ffd58bd2 SB	129	pp->res[1].name = "PCIe 0 MEM";
	130	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	131	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	132	pp->res[1].flags = IORESOURCE_MEM;
	133	if (request_resource(&iomem_resource, &pp->res[1]))
	134	panic("Request PCIe 0 Memory resource failed\n");
	135	sys->resource[1] = &pp->res[1];
	136
	137	sys->resource[2] = NULL;
	138	sys->io_offset = 0;
	139
	140	return 1;
	141	}
	142
	143	static int __init pcie1_ioresources_setup(struct pci_sys_data *sys)
	144	{
	145	struct pcie_port pp = (struct pcie_port )sys->private_data;
651c74c7 SB	146
	147	/*
	148	* IORESOURCE_IO
	149	*/
ffd58bd2 SB	150	pp->res[0].name = "PCIe 1 I/O Space";
	151	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
	152	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
	153	pp->res[0].flags = IORESOURCE_IO;
	154	if (request_resource(&ioport_resource, &pp->res[0]))
	155	panic("Request PCIe 1 IO resource failed\n");
	156	sys->resource[0] = &pp->res[0];
651c74c7 SB	157
	158	/*
	159	* IORESOURCE_MEM
	160	*/
ffd58bd2 SB	161	pp->res[1].name = "PCIe 1 MEM";
	162	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	163	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	164	pp->res[1].flags = IORESOURCE_MEM;
	165	if (request_resource(&iomem_resource, &pp->res[1]))
	166	panic("Request PCIe 1 Memory resource failed\n");
	167	sys->resource[1] = &pp->res[1];
651c74c7 SB	168
	169	sys->resource[2] = NULL;
	170	sys->io_offset = 0;
	171
ffd58bd2 SB	172	return 1;
	173	}
	174
	175	static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
	176	{
	177	extern unsigned int kirkwood_clk_ctrl;
	178	struct pcie_port *pp;
	179	int index;
	180
	181	if (nr >= num_pcie_ports)
	182	return 0;
	183
	184	index = pcie_port_map[nr];
	185	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
	186
	187	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	188	if (!pp)
	189	panic("PCIe: failed to allocate pcie_port data");
	190	sys->private_data = pp;
	191	pp->root_bus_nr = sys->busnr;
	192	spin_lock_init(&pp->conf_lock);
	193
	194	switch (index) {
	195	case 0:
	196	pp->base = (void __iomem *)PCIE_VIRT_BASE;
	197	pp->irq = IRQ_KIRKWOOD_PCIE;
	198	kirkwood_clk_ctrl \|= CGC_PEX0;
	199	pcie0_ioresources_setup(sys);
	200	break;
	201	case 1:
	202	pp->base = (void __iomem *)PCIE1_VIRT_BASE;
	203	pp->irq = IRQ_KIRKWOOD_PCIE1;
	204	kirkwood_clk_ctrl \|= CGC_PEX1;
	205	pcie1_ioresources_setup(sys);
	206	break;
	207	default:
	208	panic("PCIe setup: invalid controller");
	209	}
	210
	211	/*
	212	* Generic PCIe unit setup.
	213	*/
	214	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	215
	216	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
e8b2b7ba	217
651c74c7 SB	218	return 1;
	219	}
	220
	221	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	222	{
	223	/*
	224	* Prevent enumeration of root complex.
	225	*/
	226	if (dev->bus->parent == NULL && dev->devfn == 0) {
	227	int i;
	228
	229	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	230	dev->resource[i].start = 0;
	231	dev->resource[i].end = 0;
	232	dev->resource[i].flags = 0;
	233	}
	234	}
	235	}
	236	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	237
	238	static struct pci_bus __init *
	239	kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
	240	{
	241	struct pci_bus *bus;
	242
ffd58bd2	243	if (nr < num_pcie_ports) {
651c74c7 SB	244	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	245	} else {
	246	bus = NULL;
	247	BUG();
	248	}
	249
	250	return bus;
	251	}
	252
	253	static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	254	{
ffd58bd2 SB	255	struct pcie_port *pp = bus_to_port(dev->bus);
	256
	257	return pp->irq;
651c74c7 SB	258	}
	259
	260	static struct hw_pci kirkwood_pci __initdata = {
651c74c7 SB	261	.swizzle = pci_std_swizzle,
	262	.setup = kirkwood_pcie_setup,
	263	.scan = kirkwood_pcie_scan_bus,
	264	.map_irq = kirkwood_pcie_map_irq,
	265	};
	266
ffd58bd2 SB	267	static void __init add_pcie_port(int index, unsigned long base)
	268	{
	269	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
	270
	271	if (orion_pcie_link_up((void __iomem *)base)) {
	272	printk(KERN_INFO "link up\n");
	273	pcie_port_map[num_pcie_ports++] = index;
	274	} else
	275	printk(KERN_INFO "link down, ignoring\n");
	276	}
	277
	278	void __init kirkwood_pcie_init(unsigned int portmask)
651c74c7	279	{
ffd58bd2 SB	280	if (portmask & KW_PCIE0)
	281	add_pcie_port(0, PCIE_VIRT_BASE);
	282
	283	if (portmask & KW_PCIE1)
	284	add_pcie_port(1, PCIE1_VIRT_BASE);
	285
	286	kirkwood_pci.nr_controllers = num_pcie_ports;
651c74c7 SB	287	pci_common_init(&kirkwood_pci);
651c74c7 SB	288	}