Merge branch 'kirkwood/boards' of git://git.infradead.org/users/jcooper/linux into...
[deliverable/linux.git] / arch / arm / mach-kirkwood / pcie.c
CommitLineData
651c74c7
SB
1/*
2 * arch/arm/mach-kirkwood/pcie.c
3 *
4 * PCIe functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
5a0e3ad6 13#include <linux/slab.h>
27e53cfb 14#include <linux/clk.h>
cc22b4c1 15#include <video/vga.h>
6e5c11a1 16#include <asm/irq.h>
651c74c7 17#include <asm/mach/pci.h>
6f088f1d 18#include <plat/pcie.h>
e8b2b7ba 19#include <mach/bridge-regs.h>
45173d5e 20#include <plat/addr-map.h>
651c74c7
SB
21#include "common.h"
22
27e53cfb
AL
23static void kirkwood_enable_pcie_clk(const char *port)
24{
25 struct clk *clk;
26
27 clk = clk_get_sys("pcie", port);
28 if (IS_ERR(clk)) {
29 printk(KERN_ERR "PCIE clock %s missing\n", port);
30 return;
31 }
32 clk_prepare_enable(clk);
33 clk_put(clk);
34}
35
36/* This function is called very early in the boot when probing the
37 hardware to determine what we actually are, and what rate tclk is
38 ticking at. Hence calling kirkwood_enable_pcie_clk() is not
39 possible since the clk tree has not been created yet. */
0e0cdd37
EC
40void kirkwood_enable_pcie(void)
41{
42 u32 curr = readl(CLOCK_GATING_CTRL);
43 if (!(curr & CGC_PEX0))
44 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
45}
46
98d9986c 47void kirkwood_pcie_id(u32 *dev, u32 *rev)
ffd58bd2 48{
0e0cdd37 49 kirkwood_enable_pcie();
ffd58bd2
SB
50 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
51 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
52}
651c74c7 53
ffd58bd2
SB
54struct pcie_port {
55 u8 root_bus_nr;
56 void __iomem *base;
57 spinlock_t conf_lock;
58 int irq;
2bb08085 59 struct resource res;
ffd58bd2 60};
651c74c7 61
ffd58bd2
SB
62static int pcie_port_map[2];
63static int num_pcie_ports;
64
ffd58bd2 65static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
651c74c7
SB
66{
67 /*
68 * Don't go out when trying to access --
69 * 1. nonexisting device on local bus
70 * 2. where there's no device connected (no link)
71 */
ffd58bd2 72 if (bus == pp->root_bus_nr && dev == 0)
651c74c7
SB
73 return 1;
74
ffd58bd2 75 if (!orion_pcie_link_up(pp->base))
651c74c7
SB
76 return 0;
77
ffd58bd2 78 if (bus == pp->root_bus_nr && dev != 1)
651c74c7
SB
79 return 0;
80
81 return 1;
82}
83
84
85/*
86 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
87 * and then reading the PCIE_CONF_DATA register. Need to make sure these
88 * transactions are atomic.
89 */
651c74c7
SB
90
91static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
92 int size, u32 *val)
93{
43ba990b
RK
94 struct pci_sys_data *sys = bus->sysdata;
95 struct pcie_port *pp = sys->private_data;
651c74c7
SB
96 unsigned long flags;
97 int ret;
98
ffd58bd2 99 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
651c74c7
SB
100 *val = 0xffffffff;
101 return PCIBIOS_DEVICE_NOT_FOUND;
102 }
103
ffd58bd2
SB
104 spin_lock_irqsave(&pp->conf_lock, flags);
105 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
106 spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7
SB
107
108 return ret;
109}
110
111static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
112 int where, int size, u32 val)
113{
43ba990b
RK
114 struct pci_sys_data *sys = bus->sysdata;
115 struct pcie_port *pp = sys->private_data;
651c74c7
SB
116 unsigned long flags;
117 int ret;
118
ffd58bd2 119 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
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SB
120 return PCIBIOS_DEVICE_NOT_FOUND;
121
ffd58bd2
SB
122 spin_lock_irqsave(&pp->conf_lock, flags);
123 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
124 spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7
SB
125
126 return ret;
127}
128
129static struct pci_ops pcie_ops = {
130 .read = pcie_rd_conf,
131 .write = pcie_wr_conf,
132};
133
a87182b3 134static void __init pcie0_ioresources_init(struct pcie_port *pp)
651c74c7 135{
a87182b3
NP
136 pp->base = (void __iomem *)PCIE_VIRT_BASE;
137 pp->irq = IRQ_KIRKWOOD_PCIE;
651c74c7 138
651c74c7 139 /*
ffd58bd2 140 * IORESOURCE_MEM
651c74c7 141 */
2bb08085
RH
142 pp->res.name = "PCIe 0 MEM";
143 pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
144 pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
145 pp->res.flags = IORESOURCE_MEM;
ffd58bd2
SB
146}
147
a87182b3 148static void __init pcie1_ioresources_init(struct pcie_port *pp)
ffd58bd2 149{
a87182b3
NP
150 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
151 pp->irq = IRQ_KIRKWOOD_PCIE1;
651c74c7 152
651c74c7
SB
153 /*
154 * IORESOURCE_MEM
155 */
2bb08085
RH
156 pp->res.name = "PCIe 1 MEM";
157 pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
158 pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
159 pp->res.flags = IORESOURCE_MEM;
ffd58bd2
SB
160}
161
162static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
163{
ffd58bd2
SB
164 struct pcie_port *pp;
165 int index;
166
167 if (nr >= num_pcie_ports)
168 return 0;
169
170 index = pcie_port_map[nr];
171 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
172
173 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
174 if (!pp)
175 panic("PCIe: failed to allocate pcie_port data");
176 sys->private_data = pp;
177 pp->root_bus_nr = sys->busnr;
178 spin_lock_init(&pp->conf_lock);
179
180 switch (index) {
181 case 0:
27e53cfb 182 kirkwood_enable_pcie_clk("0");
a87182b3 183 pcie0_ioresources_init(pp);
2bb08085 184 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
ffd58bd2
SB
185 break;
186 case 1:
27e53cfb 187 kirkwood_enable_pcie_clk("1");
a87182b3 188 pcie1_ioresources_init(pp);
2bb08085 189 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
ffd58bd2
SB
190 break;
191 default:
a87182b3 192 panic("PCIe setup: invalid controller %d", index);
ffd58bd2
SB
193 }
194
2bb08085 195 if (request_resource(&iomem_resource, &pp->res))
a87182b3
NP
196 panic("Request PCIe%d Memory resource failed\n", index);
197
2bb08085 198 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
a87182b3 199
ffd58bd2
SB
200 /*
201 * Generic PCIe unit setup.
202 */
203 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
204
63a9332b 205 orion_pcie_setup(pp->base);
e8b2b7ba 206
651c74c7
SB
207 return 1;
208}
209
210static void __devinit rc_pci_fixup(struct pci_dev *dev)
211{
212 /*
213 * Prevent enumeration of root complex.
214 */
215 if (dev->bus->parent == NULL && dev->devfn == 0) {
216 int i;
217
218 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
219 dev->resource[i].start = 0;
220 dev->resource[i].end = 0;
221 dev->resource[i].flags = 0;
222 }
223 }
224}
225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
226
227static struct pci_bus __init *
228kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
229{
230 struct pci_bus *bus;
231
ffd58bd2 232 if (nr < num_pcie_ports) {
37d15909
BH
233 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
234 &sys->resources);
651c74c7
SB
235 } else {
236 bus = NULL;
237 BUG();
238 }
239
240 return bus;
241}
242
d5341942
RB
243static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
244 u8 pin)
651c74c7 245{
43ba990b
RK
246 struct pci_sys_data *sys = dev->sysdata;
247 struct pcie_port *pp = sys->private_data;
ffd58bd2
SB
248
249 return pp->irq;
651c74c7
SB
250}
251
252static struct hw_pci kirkwood_pci __initdata = {
651c74c7
SB
253 .setup = kirkwood_pcie_setup,
254 .scan = kirkwood_pcie_scan_bus,
255 .map_irq = kirkwood_pcie_map_irq,
256};
257
ffd58bd2
SB
258static void __init add_pcie_port(int index, unsigned long base)
259{
260 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
261
262 if (orion_pcie_link_up((void __iomem *)base)) {
263 printk(KERN_INFO "link up\n");
264 pcie_port_map[num_pcie_ports++] = index;
265 } else
266 printk(KERN_INFO "link down, ignoring\n");
267}
268
269void __init kirkwood_pcie_init(unsigned int portmask)
651c74c7 270{
cc22b4c1
RH
271 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
272
ffd58bd2
SB
273 if (portmask & KW_PCIE0)
274 add_pcie_port(0, PCIE_VIRT_BASE);
275
276 if (portmask & KW_PCIE1)
277 add_pcie_port(1, PCIE1_VIRT_BASE);
278
279 kirkwood_pci.nr_controllers = num_pcie_ports;
651c74c7
SB
280 pci_common_init(&kirkwood_pci);
281}
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