[deliverable/linux.git] / arch / arm / mach-ks8695 / irq.c

/*
 * arch/arm/mach-ks8695/irq.c
 *
 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
 * Copyright (C) 2006 Simtec Electronics
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#include <asm/mach/irq.h>

#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>

static void ks8695_irq_mask(struct irq_data *d)
{
	unsigned long inten;

	inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
	inten &= ~(1 << d->irq);

	__raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
}

static void ks8695_irq_unmask(struct irq_data *d)
{
	unsigned long inten;

	inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
	inten |= (1 << d->irq);

	__raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
}

static void ks8695_irq_ack(struct irq_data *d)
{
	__raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST);
}


static struct irq_chip ks8695_irq_level_chip;
static struct irq_chip ks8695_irq_edge_chip;


static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned long ctrl, mode;
	unsigned short level_triggered = 0;

	ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);

	switch (type) {
		case IRQ_TYPE_LEVEL_HIGH:
			mode = IOPC_TM_HIGH;
			level_triggered = 1;
			break;
		case IRQ_TYPE_LEVEL_LOW:
			mode = IOPC_TM_LOW;
			level_triggered = 1;
			break;
		case IRQ_TYPE_EDGE_RISING:
			mode = IOPC_TM_RISING;
			break;
		case IRQ_TYPE_EDGE_FALLING:
			mode = IOPC_TM_FALLING;
			break;
		case IRQ_TYPE_EDGE_BOTH:
			mode = IOPC_TM_EDGE;
			break;
		default:
			return -EINVAL;
	}

	switch (d->irq) {
		case KS8695_IRQ_EXTERN0:
			ctrl &= ~IOPC_IOEINT0TM;
			ctrl |= IOPC_IOEINT0_MODE(mode);
			break;
		case KS8695_IRQ_EXTERN1:
			ctrl &= ~IOPC_IOEINT1TM;
			ctrl |= IOPC_IOEINT1_MODE(mode);
			break;
		case KS8695_IRQ_EXTERN2:
			ctrl &= ~IOPC_IOEINT2TM;
			ctrl |= IOPC_IOEINT2_MODE(mode);
			break;
		case KS8695_IRQ_EXTERN3:
			ctrl &= ~IOPC_IOEINT3TM;
			ctrl |= IOPC_IOEINT3_MODE(mode);
			break;
		default:
			return -EINVAL;
	}

	if (level_triggered) {
		irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
					 handle_level_irq);
	}
	else {
		irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
					 handle_edge_irq);
	}

	__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
	return 0;
}

static struct irq_chip ks8695_irq_level_chip = {
	.irq_ack	= ks8695_irq_mask,
	.irq_mask	= ks8695_irq_mask,
	.irq_unmask	= ks8695_irq_unmask,
	.irq_set_type	= ks8695_irq_set_type,
};

static struct irq_chip ks8695_irq_edge_chip = {
	.irq_ack	= ks8695_irq_ack,
	.irq_mask	= ks8695_irq_mask,
	.irq_unmask	= ks8695_irq_unmask,
	.irq_set_type	= ks8695_irq_set_type,
};

void __init ks8695_init_irq(void)
{
	unsigned int irq;

	/* Disable all interrupts initially */
	__raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC);
	__raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN);

	for (irq = 0; irq < NR_IRQS; irq++) {
		switch (irq) {
			/* Level-triggered interrupts */
			case KS8695_IRQ_BUS_ERROR:
			case KS8695_IRQ_UART_MODEM_STATUS:
			case KS8695_IRQ_UART_LINE_STATUS:
			case KS8695_IRQ_UART_RX:
			case KS8695_IRQ_COMM_TX:
			case KS8695_IRQ_COMM_RX:
				irq_set_chip_and_handler(irq,
							 &ks8695_irq_level_chip,
							 handle_level_irq);
				break;

			/* Edge-triggered interrupts */
			default:
				/* clear pending bit */
				ks8695_irq_ack(irq_get_irq_data(irq));
				irq_set_chip_and_handler(irq,
							 &ks8695_irq_edge_chip,
							 handle_edge_irq);
		}

		irq_clear_status_flags(irq, IRQ_NOREQUEST);
	}
}
Commit	Line	Data
c53c9cf6 AV	1	/*
	2	* arch/arm/mach-ks8695/irq.c
	3	*
	4	* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
	5	* Copyright (C) 2006 Simtec Electronics
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/init.h>
	23	#include <linux/module.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/ioport.h>
edbaa603	26	#include <linux/device.h>
fced80c7	27	#include <linux/io.h>
c53c9cf6	28
a09e64fb	29	#include <mach/hardware.h>
c53c9cf6	30	#include <asm/irq.h>
c53c9cf6 AV	31
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/regs-irq.h>
a09e64fb RK	35	#include <mach/regs-gpio.h>
c53c9cf6	36
3cdb791b	37	static void ks8695_irq_mask(struct irq_data *d)
c53c9cf6 AV	38	{
	39	unsigned long inten;
	40
	41	inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
3cdb791b	42	inten &= ~(1 << d->irq);
c53c9cf6 AV	43
	44	__raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
	45	}
	46
3cdb791b	47	static void ks8695_irq_unmask(struct irq_data *d)
c53c9cf6 AV	48	{
	49	unsigned long inten;
	50
	51	inten = __raw_readl(KS8695_IRQ_VA + KS8695_INTEN);
3cdb791b	52	inten \|= (1 << d->irq);
c53c9cf6 AV	53
	54	__raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN);
	55	}
	56
3cdb791b	57	static void ks8695_irq_ack(struct irq_data *d)
c53c9cf6	58	{
3cdb791b	59	__raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST);
c53c9cf6 AV	60	}
	61
	62
	63	static struct irq_chip ks8695_irq_level_chip;
	64	static struct irq_chip ks8695_irq_edge_chip;
	65
	66
3cdb791b	67	static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
c53c9cf6 AV	68	{
	69	unsigned long ctrl, mode;
	70	unsigned short level_triggered = 0;
	71
	72	ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC);
	73
	74	switch (type) {
6cab4860	75	case IRQ_TYPE_LEVEL_HIGH:
c53c9cf6 AV	76	mode = IOPC_TM_HIGH;
	77	level_triggered = 1;
	78	break;
6cab4860	79	case IRQ_TYPE_LEVEL_LOW:
c53c9cf6 AV	80	mode = IOPC_TM_LOW;
	81	level_triggered = 1;
	82	break;
6cab4860	83	case IRQ_TYPE_EDGE_RISING:
c53c9cf6 AV	84	mode = IOPC_TM_RISING;
c53c9cf6 AV	85	break;
6cab4860	86	case IRQ_TYPE_EDGE_FALLING:
c53c9cf6 AV	87	mode = IOPC_TM_FALLING;
c53c9cf6 AV	88	break;
6cab4860	89	case IRQ_TYPE_EDGE_BOTH:
c53c9cf6 AV	90	mode = IOPC_TM_EDGE;
	91	break;
	92	default:
	93	return -EINVAL;
	94	}
	95
3cdb791b	96	switch (d->irq) {
c53c9cf6 AV	97	case KS8695_IRQ_EXTERN0:
	98	ctrl &= ~IOPC_IOEINT0TM;
	99	ctrl \|= IOPC_IOEINT0_MODE(mode);
	100	break;
	101	case KS8695_IRQ_EXTERN1:
	102	ctrl &= ~IOPC_IOEINT1TM;
	103	ctrl \|= IOPC_IOEINT1_MODE(mode);
	104	break;
	105	case KS8695_IRQ_EXTERN2:
	106	ctrl &= ~IOPC_IOEINT2TM;
	107	ctrl \|= IOPC_IOEINT2_MODE(mode);
	108	break;
	109	case KS8695_IRQ_EXTERN3:
	110	ctrl &= ~IOPC_IOEINT3TM;
	111	ctrl \|= IOPC_IOEINT3_MODE(mode);
	112	break;
	113	default:
	114	return -EINVAL;
	115	}
	116
	117	if (level_triggered) {
f38c02f3 TG	118	irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
f38c02f3 TG	119	handle_level_irq);
c53c9cf6 AV	120	}
c53c9cf6 AV	121	else {
f38c02f3 TG	122	irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
f38c02f3 TG	123	handle_edge_irq);
c53c9cf6 AV	124	}
	125
	126	__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
	127	return 0;
	128	}
	129
	130	static struct irq_chip ks8695_irq_level_chip = {
3cdb791b LB	131	.irq_ack = ks8695_irq_mask,
	132	.irq_mask = ks8695_irq_mask,
	133	.irq_unmask = ks8695_irq_unmask,
	134	.irq_set_type = ks8695_irq_set_type,
c53c9cf6 AV	135	};
	136
	137	static struct irq_chip ks8695_irq_edge_chip = {
3cdb791b LB	138	.irq_ack = ks8695_irq_ack,
	139	.irq_mask = ks8695_irq_mask,
	140	.irq_unmask = ks8695_irq_unmask,
	141	.irq_set_type = ks8695_irq_set_type,
c53c9cf6 AV	142	};
	143
	144	void __init ks8695_init_irq(void)
	145	{
	146	unsigned int irq;
	147
	148	/* Disable all interrupts initially */
	149	__raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC);
	150	__raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN);
	151
	152	for (irq = 0; irq < NR_IRQS; irq++) {
	153	switch (irq) {
	154	/* Level-triggered interrupts */
	155	case KS8695_IRQ_BUS_ERROR:
	156	case KS8695_IRQ_UART_MODEM_STATUS:
	157	case KS8695_IRQ_UART_LINE_STATUS:
	158	case KS8695_IRQ_UART_RX:
	159	case KS8695_IRQ_COMM_TX:
	160	case KS8695_IRQ_COMM_RX:
f38c02f3 TG	161	irq_set_chip_and_handler(irq,
	162	&ks8695_irq_level_chip,
	163	handle_level_irq);
c53c9cf6 AV	164	break;
	165
	166	/* Edge-triggered interrupts */
	167	default:
3cdb791b LB	168	/* clear pending bit */
3cdb791b LB	169	ks8695_irq_ack(irq_get_irq_data(irq));
f38c02f3 TG	170	irq_set_chip_and_handler(irq,
	171	&ks8695_irq_edge_chip,
	172	handle_edge_irq);
c53c9cf6 AV	173	}
c53c9cf6 AV	174
e8d36d5d	175	irq_clear_status_flags(irq, IRQ_NOREQUEST);
c53c9cf6 AV	176	}
c53c9cf6 AV	177	}