[ARM] Remove compatibility layer for ARM irqs
[deliverable/linux.git] / arch / arm / mach-lh7a40x / arch-kev7a400.c
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1/* arch/arm/mach-lh7a40x/arch-kev7a400.c
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/tty.h>
12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/interrupt.h>
15
16#include <asm/hardware.h>
17#include <asm/setup.h>
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/irq.h>
21#include <asm/mach/irq.h>
22#include <asm/mach/map.h>
23
24#include "common.h"
25
26 /* This function calls the board specific IRQ initialization function. */
27
28static struct map_desc kev7a400_io_desc[] __initdata = {
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DS
29 {
30 .virtual = IO_VIRT,
31 .pfn = __phys_to_pfn(IO_PHYS),
32 .length = IO_SIZE,
33 .type = MT_DEVICE
34 }, {
35 .virtual = CPLD_VIRT,
36 .pfn = __phys_to_pfn(CPLD_PHYS),
37 .length = CPLD_SIZE,
38 .type = MT_DEVICE
39 }
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40};
41
42void __init kev7a400_map_io(void)
43{
44 iotable_init (kev7a400_io_desc, ARRAY_SIZE (kev7a400_io_desc));
45}
46
47static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
48
49static void kev7a400_ack_cpld_irq (u32 irq)
50{
51 CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD);
52}
53
54static void kev7a400_mask_cpld_irq (u32 irq)
55{
56 CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD));
57 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
58}
59
60static void kev7a400_unmask_cpld_irq (u32 irq)
61{
62 CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD);
63 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
64}
65
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DB
66static struct irq_chip kev7a400_cpld_chip = {
67 .name = "CPLD",
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68 .ack = kev7a400_ack_cpld_irq,
69 .mask = kev7a400_mask_cpld_irq,
70 .unmask = kev7a400_unmask_cpld_irq,
71};
72
73
10dd5ce2 74static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
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75{
76 u32 mask = CPLD_LATCHED_INTS;
77 irq = IRQ_KEV7A400_CPLD;
78 for (; mask; mask >>= 1, ++irq) {
79 if (mask & 1)
0cd61b68 80 desc[irq].handle (irq, desc);
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81 }
82}
83
84void __init lh7a40x_init_board_irq (void)
85{
86 int irq;
87
88 for (irq = IRQ_KEV7A400_CPLD;
89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
90 set_irq_chip (irq, &kev7a400_cpld_chip);
10dd5ce2 91 set_irq_handler (irq, handle_edge_irq);
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92 set_irq_flags (irq, IRQF_VALID);
93 }
94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
95
96 /* Clear all CPLD interrupts */
97 CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
98
99 GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
100 barrier();
101
102#if 0
103 GPIO_INTTYPE1
104 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
105 GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
106 GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
107 GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
108
109 init_FIQ();
110#endif
111}
112
113MACHINE_START (KEV7A400, "Sharp KEV7a400")
e9dea0c6 114 /* Maintainer: Marc Singer */
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115 .phys_io = 0x80000000,
116 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
117 .boot_params = 0xc0000100,
118 .map_io = kev7a400_map_io,
119 .init_irq = lh7a400_init_irq,
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120 .timer = &lh7a40x_timer,
121MACHINE_END
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