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[deliverable/linux.git] / arch / arm / mach-lpc32xx / clock.c
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b9cc4bf6
KW		 1/*
2 * arch/arm/mach-lpc32xx/clock.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19/*
20 * LPC32xx clock management driver overview
21 *
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
29 *
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
35 * disabled normally.
36 * 32KHz oscillator*
37 * / | \
38 * RTC* PLL397^ TOUCH
39 * /
40 * Main oscillator^ /
41 * | \ /
42 * | SYSCLK&
43 * | \
44 * | \
45 * USB_PLL HCLK_PLL&
46 * | | |
47 * USB host/device PCLK& |
48 * | |
49 * Peripherals
50 *
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
59 *
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
67 *
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
76 * to an external pin.
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
78 * this driver.
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
83 */
84
8998316c 85#include <linux/export.h>
b9cc4bf6
KW		 86#include <linux/kernel.h>
87#include <linux/list.h>
88#include <linux/errno.h>
89#include <linux/device.h>
48a5dedf 90#include <linux/delay.h>
b9cc4bf6
KW		 91#include <linux/err.h>
92#include <linux/clk.h>
93#include <linux/amba/bus.h>
94#include <linux/amba/clcd.h>
6d803ba7 95#include <linux/clkdev.h>
b9cc4bf6
KW		 96
97#include <mach/hardware.h>
b9cc4bf6
KW		 98#include <mach/platform.h>
99#include "clock.h"
100#include "common.h"
101
b8451862
RS		 102static DEFINE_SPINLOCK(global_clkregs_lock);
103
48a5dedf
RS		 104static int usb_pll_enable, usb_pll_valid;
105
b9cc4bf6
KW		 106static struct clk clk_armpll;
107static struct clk clk_usbpll;
b9cc4bf6
KW		 108
109/*
110 * Post divider values for PLLs based on selected register value
111 */
112static const u32 pll_postdivs[4] = {1, 2, 4, 8};
113
114static unsigned long local_return_parent_rate(struct clk *clk)
115{
116 /*
117 * If a clock has a rate of 0, then it inherits it's parent
118 * clock rate
119 */
120 while (clk->rate == 0)
121 clk = clk->parent;
122
123 return clk->rate;
124}
125
126/* 32KHz clock has a fixed rate and is not stoppable */
127static struct clk osc_32KHz = {
128 .rate = LPC32XX_CLOCK_OSC_FREQ,
129 .get_rate = local_return_parent_rate,
130};
131
132static int local_pll397_enable(struct clk *clk, int enable)
133{
134 u32 reg;
f40a6818 135 unsigned long timeout = jiffies + msecs_to_jiffies(10);
b9cc4bf6
KW		 136
137 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
138
139 if (enable == 0) {
140 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
141 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
142 } else {
143 /* Enable PLL397 */
144 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
145 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
146
147 /* Wait for PLL397 lock */
148 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
149 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
f40a6818 150 time_before(jiffies, timeout))
b9cc4bf6
KW		 151 cpu_relax();
152
153 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
154 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
155 return -ENODEV;
156 }
157
158 return 0;
159}
160
161static int local_oscmain_enable(struct clk *clk, int enable)
162{
163 u32 reg;
f40a6818 164 unsigned long timeout = jiffies + msecs_to_jiffies(10);
b9cc4bf6
KW		 165
166 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
167
168 if (enable == 0) {
169 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
170 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
171 } else {
172 /* Enable main oscillator */
173 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
174 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
175
176 /* Wait for main oscillator to start */
177 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
178 LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
f40a6818 179 time_before(jiffies, timeout))
b9cc4bf6
KW		 180 cpu_relax();
181
182 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
183 LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
184 return -ENODEV;
185 }
186
187 return 0;
188}
189
190static struct clk osc_pll397 = {
191 .parent = &osc_32KHz,
192 .enable = local_pll397_enable,
193 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
194 .get_rate = local_return_parent_rate,
195};
196
197static struct clk osc_main = {
198 .enable = local_oscmain_enable,
199 .rate = LPC32XX_MAIN_OSC_FREQ,
200 .get_rate = local_return_parent_rate,
201};
202
203static struct clk clk_sys;
204
205/*
206 * Convert a PLL register value to a PLL output frequency
207 */
208u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
209{
210 struct clk_pll_setup pllcfg;
211
212 pllcfg.cco_bypass_b15 = 0;
213 pllcfg.direct_output_b14 = 0;
214 pllcfg.fdbk_div_ctrl_b13 = 0;
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
216 pllcfg.cco_bypass_b15 = 1;
217 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
218 pllcfg.direct_output_b14 = 1;
219 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
220 pllcfg.fdbk_div_ctrl_b13 = 1;
221 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
222 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
223 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
224
225 return clk_check_pll_setup(inputclk, &pllcfg);
226}
227
228/*
229 * Setup the HCLK PLL with a PLL structure
230 */
231static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
232{
233 u32 tv, tmp = 0;
234
235 if (PllSetup->analog_on != 0)
236 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
237 if (PllSetup->cco_bypass_b15 != 0)
238 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
239 if (PllSetup->direct_output_b14 != 0)
240 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
241 if (PllSetup->fdbk_div_ctrl_b13 != 0)
242 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
243
244 tv = ffs(PllSetup->pll_p) - 1;
245 if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
246 return 0;
247
248 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
249 tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
250 tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
251
252 return tmp;
253}
254
255/*
256 * Update the ARM core PLL frequency rate variable from the actual PLL setting
257 */
258static void local_update_armpll_rate(void)
259{
260 u32 clkin, pllreg;
261
262 clkin = clk_armpll.parent->rate;
263 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
264
265 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
266}
267
268/*
269 * Find a PLL configuration for the selected input frequency
270 */
271static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
272 struct clk_pll_setup *pllsetup)
273{
274 u32 ifreq, freqtol, m, n, p, fclkout;
275
276 /* Determine frequency tolerance limits */
277 freqtol = target_freq / 250;
278 ifreq = pllin_freq;
279
280 /* Is direct bypass mode possible? */
281 if (abs(pllin_freq - target_freq) <= freqtol) {
282 pllsetup->analog_on = 0;
283 pllsetup->cco_bypass_b15 = 1;
284 pllsetup->direct_output_b14 = 1;
285 pllsetup->fdbk_div_ctrl_b13 = 1;
286 pllsetup->pll_p = pll_postdivs[0];
287 pllsetup->pll_n = 1;
288 pllsetup->pll_m = 1;
289 return clk_check_pll_setup(ifreq, pllsetup);
290 } else if (target_freq <= ifreq) {
291 pllsetup->analog_on = 0;
292 pllsetup->cco_bypass_b15 = 1;
293 pllsetup->direct_output_b14 = 0;
294 pllsetup->fdbk_div_ctrl_b13 = 1;
295 pllsetup->pll_n = 1;
296 pllsetup->pll_m = 1;
297 for (p = 0; p <= 3; p++) {
298 pllsetup->pll_p = pll_postdivs[p];
299 fclkout = clk_check_pll_setup(ifreq, pllsetup);
300 if (abs(target_freq - fclkout) <= freqtol)
301 return fclkout;
302 }
303 }
304
305 /* Is direct mode possible? */
306 pllsetup->analog_on = 1;
307 pllsetup->cco_bypass_b15 = 0;
308 pllsetup->direct_output_b14 = 1;
309 pllsetup->fdbk_div_ctrl_b13 = 0;
310 pllsetup->pll_p = pll_postdivs[0];
311 for (m = 1; m <= 256; m++) {
312 for (n = 1; n <= 4; n++) {
313 /* Compute output frequency for this value */
314 pllsetup->pll_n = n;
315 pllsetup->pll_m = m;
316 fclkout = clk_check_pll_setup(ifreq,
317 pllsetup);
318 if (abs(target_freq - fclkout) <=
319 freqtol)
320 return fclkout;
321 }
322 }
323
324 /* Is integer mode possible? */
325 pllsetup->analog_on = 1;
326 pllsetup->cco_bypass_b15 = 0;
327 pllsetup->direct_output_b14 = 0;
328 pllsetup->fdbk_div_ctrl_b13 = 1;
329 for (m = 1; m <= 256; m++) {
330 for (n = 1; n <= 4; n++) {
331 for (p = 0; p < 4; p++) {
332 /* Compute output frequency */
333 pllsetup->pll_p = pll_postdivs[p];
334 pllsetup->pll_n = n;
335 pllsetup->pll_m = m;
336 fclkout = clk_check_pll_setup(
337 ifreq, pllsetup);
338 if (abs(target_freq - fclkout) <= freqtol)
339 return fclkout;
340 }
341 }
342 }
343
344 /* Try non-integer mode */
345 pllsetup->analog_on = 1;
346 pllsetup->cco_bypass_b15 = 0;
347 pllsetup->direct_output_b14 = 0;
348 pllsetup->fdbk_div_ctrl_b13 = 0;
349 for (m = 1; m <= 256; m++) {
350 for (n = 1; n <= 4; n++) {
351 for (p = 0; p < 4; p++) {
352 /* Compute output frequency */
353 pllsetup->pll_p = pll_postdivs[p];
354 pllsetup->pll_n = n;
355 pllsetup->pll_m = m;
356 fclkout = clk_check_pll_setup(
357 ifreq, pllsetup);
358 if (abs(target_freq - fclkout) <= freqtol)
359 return fclkout;
360 }
361 }
362 }
363
364 return 0;
365}
366
367static struct clk clk_armpll = {
368 .parent = &clk_sys,
369 .get_rate = local_return_parent_rate,
370};
371
372/*
373 * Setup the USB PLL with a PLL structure
374 */
375static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
376{
377 u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
378
379 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
380 reg |= tmp;
381 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
382
383 return clk_check_pll_setup(clk_usbpll.parent->rate,
384 pHCLKPllSetup);
385}
386
387static int local_usbpll_enable(struct clk *clk, int enable)
388{
389 u32 reg;
48a5dedf
RS		 390 int ret = 0;
391 unsigned long timeout = jiffies + msecs_to_jiffies(20);
b9cc4bf6
KW		 392
393 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
394
48a5dedf
RS		 395 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
396 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
397 LPC32XX_CLKPWR_USB_CTRL);
398 __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
399 LPC32XX_CLKPWR_USB_CTRL);
400
401 if (enable && usb_pll_valid && usb_pll_enable) {
402 ret = -ENODEV;
403 /*
404 * If the PLL rate has been previously set, then the rate
405 * in the PLL register is valid and can be enabled here.
406 * Otherwise, it needs to be enabled as part of setrate.
407 */
408
409 /*
410 * Gate clock into PLL
411 */
b9cc4bf6
KW		 412 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
413 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
414
48a5dedf
RS		 415 /*
416 * Enable PLL
417 */
418 reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
419 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
420
421 /*
422 * Wait for PLL to lock
423 */
f40a6818 424 while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
b9cc4bf6
KW		 425 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
426 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
427 ret = 0;
48a5dedf
RS		 428 else
429 udelay(10);
b9cc4bf6
KW		 430 }
431
48a5dedf
RS		 432 /*
433 * Gate clock from PLL if PLL is locked
434 */
b9cc4bf6 435 if (ret == 0) {
48a5dedf
RS		 436 __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
437 LPC32XX_CLKPWR_USB_CTRL);
438 } else {
439 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
440 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
441 LPC32XX_CLKPWR_USB_CTRL);
b9cc4bf6 442 }
48a5dedf
RS		 443 } else if ((enable == 0) && usb_pll_valid && usb_pll_enable) {
444 usb_pll_valid = 0;
445 usb_pll_enable = 0;
b9cc4bf6
KW		 446 }
447
448 return ret;
449}
450
451static unsigned long local_usbpll_round_rate(struct clk *clk,
452 unsigned long rate)
453{
454 u32 clkin, usbdiv;
455 struct clk_pll_setup pllsetup;
456
457 /*
458 * Unlike other clocks, this clock has a KHz input rate, so bump
459 * it up to work with the PLL function
460 */
461 rate = rate * 1000;
462
48a5dedf 463 clkin = clk->get_rate(clk);
b9cc4bf6
KW		 464 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
465 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
466 clkin = clkin / usbdiv;
467
468 /* Try to find a good rate setup */
469 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
470 return 0;
471
472 return clk_check_pll_setup(clkin, &pllsetup);
473}
474
475static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
476{
48a5dedf
RS		 477 int ret = -ENODEV;
478 u32 clkin, usbdiv;
b9cc4bf6
KW		 479 struct clk_pll_setup pllsetup;
480
481 /*
482 * Unlike other clocks, this clock has a KHz input rate, so bump
483 * it up to work with the PLL function
484 */
485 rate = rate * 1000;
486
48a5dedf 487 clkin = clk->get_rate(clk->parent);
b9cc4bf6
KW		 488 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
489 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
490 clkin = clkin / usbdiv;
491
492 /* Try to find a good rate setup */
493 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
494 return -EINVAL;
495
48a5dedf
RS		 496 /*
497 * Disable PLL clocks during PLL change
498 */
b9cc4bf6 499 local_usbpll_enable(clk, 0);
48a5dedf 500 pllsetup.analog_on = 0;
b9cc4bf6
KW		 501 local_clk_usbpll_setup(&pllsetup);
502
48a5dedf
RS		 503 /*
504 * Start USB PLL and check PLL status
505 */
506
507 usb_pll_valid = 1;
508 usb_pll_enable = 1;
b9cc4bf6 509
48a5dedf
RS		 510 ret = local_usbpll_enable(clk, 1);
511 if (ret >= 0)
512 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
b9cc4bf6 513
48a5dedf 514 return ret;
b9cc4bf6
KW		 515}
516
517static struct clk clk_usbpll = {
518 .parent = &osc_main,
519 .set_rate = local_usbpll_set_rate,
520 .enable = local_usbpll_enable,
521 .rate = 48000, /* In KHz */
522 .get_rate = local_return_parent_rate,
523 .round_rate = local_usbpll_round_rate,
524};
525
526static u32 clk_get_hclk_div(void)
527{
528 static const u32 hclkdivs[4] = {1, 2, 4, 4};
529 return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
530 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
531}
532
533static struct clk clk_hclk = {
534 .parent = &clk_armpll,
535 .get_rate = local_return_parent_rate,
536};
537
538static struct clk clk_pclk = {
539 .parent = &clk_armpll,
540 .get_rate = local_return_parent_rate,
541};
542
543static int local_onoff_enable(struct clk *clk, int enable)
544{
545 u32 tmp;
546
547 tmp = __raw_readl(clk->enable_reg);
548
549 if (enable == 0)
550 tmp &= ~clk->enable_mask;
551 else
552 tmp |= clk->enable_mask;
553
554 __raw_writel(tmp, clk->enable_reg);
555
556 return 0;
557}
558
559/* Peripheral clock sources */
560static struct clk clk_timer0 = {
561 .parent = &clk_pclk,
562 .enable = local_onoff_enable,
563 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
564 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
565 .get_rate = local_return_parent_rate,
566};
567static struct clk clk_timer1 = {
568 .parent = &clk_pclk,
569 .enable = local_onoff_enable,
570 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
571 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
572 .get_rate = local_return_parent_rate,
573};
574static struct clk clk_timer2 = {
575 .parent = &clk_pclk,
576 .enable = local_onoff_enable,
577 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
578 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
579 .get_rate = local_return_parent_rate,
580};
581static struct clk clk_timer3 = {
582 .parent = &clk_pclk,
583 .enable = local_onoff_enable,
584 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
585 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
586 .get_rate = local_return_parent_rate,
587};
84cee34d
AB		 588static struct clk clk_mpwm = {
589 .parent = &clk_pclk,
590 .enable = local_onoff_enable,
591 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
592 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
593 .get_rate = local_return_parent_rate,
594};
b9cc4bf6
KW		 595static struct clk clk_wdt = {
596 .parent = &clk_pclk,
597 .enable = local_onoff_enable,
598 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
599 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
600 .get_rate = local_return_parent_rate,
601};
602static struct clk clk_vfp9 = {
603 .parent = &clk_pclk,
604 .enable = local_onoff_enable,
605 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
606 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
607 .get_rate = local_return_parent_rate,
608};
609static struct clk clk_dma = {
610 .parent = &clk_hclk,
611 .enable = local_onoff_enable,
612 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
613 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
614 .get_rate = local_return_parent_rate,
615};
616
1f37a3a3
APS		 617static struct clk clk_pwm = {
618 .parent = &clk_pclk,
619 .enable = local_onoff_enable,
620 .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL,
621 .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
622 LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
623 LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
624 LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
625 LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
626 LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
627 .get_rate = local_return_parent_rate,
628};
629
b9cc4bf6
KW		 630static struct clk clk_uart3 = {
631 .parent = &clk_pclk,
632 .enable = local_onoff_enable,
633 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
634 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
635 .get_rate = local_return_parent_rate,
636};
637
638static struct clk clk_uart4 = {
639 .parent = &clk_pclk,
640 .enable = local_onoff_enable,
641 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
642 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
643 .get_rate = local_return_parent_rate,
644};
645
646static struct clk clk_uart5 = {
647 .parent = &clk_pclk,
648 .enable = local_onoff_enable,
649 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
650 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
651 .get_rate = local_return_parent_rate,
652};
653
654static struct clk clk_uart6 = {
655 .parent = &clk_pclk,
656 .enable = local_onoff_enable,
657 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
658 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
659 .get_rate = local_return_parent_rate,
660};
661
662static struct clk clk_i2c0 = {
663 .parent = &clk_hclk,
664 .enable = local_onoff_enable,
665 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
666 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
667 .get_rate = local_return_parent_rate,
668};
669
670static struct clk clk_i2c1 = {
671 .parent = &clk_hclk,
672 .enable = local_onoff_enable,
673 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
674 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
675 .get_rate = local_return_parent_rate,
676};
677
678static struct clk clk_i2c2 = {
679 .parent = &clk_pclk,
680 .enable = local_onoff_enable,
681 .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
682 .enable_mask = 0x4,
683 .get_rate = local_return_parent_rate,
684};
685
686static struct clk clk_ssp0 = {
687 .parent = &clk_hclk,
688 .enable = local_onoff_enable,
689 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
690 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
691 .get_rate = local_return_parent_rate,
692};
693
694static struct clk clk_ssp1 = {
695 .parent = &clk_hclk,
696 .enable = local_onoff_enable,
697 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
698 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
699 .get_rate = local_return_parent_rate,
700};
701
702static struct clk clk_kscan = {
703 .parent = &osc_32KHz,
704 .enable = local_onoff_enable,
705 .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
706 .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
707 .get_rate = local_return_parent_rate,
708};
709
710static struct clk clk_nand = {
711 .parent = &clk_hclk,
712 .enable = local_onoff_enable,
713 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
b27f4822
RS		 714 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
715 LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
b9cc4bf6
KW		 716 .get_rate = local_return_parent_rate,
717};
718
b27f4822
RS		 719static struct clk clk_nand_mlc = {
720 .parent = &clk_hclk,
721 .enable = local_onoff_enable,
722 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
723 .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
724 LPC32XX_CLKPWR_NANDCLK_DMA_INT |
725 LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
726 .get_rate = local_return_parent_rate,
727};
728
b9cc4bf6
KW		 729static struct clk clk_i2s0 = {
730 .parent = &clk_hclk,
731 .enable = local_onoff_enable,
732 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
733 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
734 .get_rate = local_return_parent_rate,
735};
736
737static struct clk clk_i2s1 = {
738 .parent = &clk_hclk,
739 .enable = local_onoff_enable,
740 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
df072717
APS		 741 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
742 LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
b9cc4bf6
KW		 743 .get_rate = local_return_parent_rate,
744};
745
746static struct clk clk_net = {
747 .parent = &clk_hclk,
748 .enable = local_onoff_enable,
749 .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
750 .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
751 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
752 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
753 .get_rate = local_return_parent_rate,
754};
755
756static struct clk clk_rtc = {
757 .parent = &osc_32KHz,
758 .rate = 1, /* 1 Hz */
759 .get_rate = local_return_parent_rate,
760};
761
a408e8f4
APS		 762static int local_usb_enable(struct clk *clk, int enable)
763{
764 u32 tmp;
765
766 if (enable) {
767 /* Set up I2C pull levels */
768 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
769 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE;
770 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
771 }
772
773 return local_onoff_enable(clk, enable);
774}
775
b9cc4bf6
KW		 776static struct clk clk_usbd = {
777 .parent = &clk_usbpll,
a408e8f4 778 .enable = local_usb_enable,
b9cc4bf6
KW		 779 .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
780 .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
781 .get_rate = local_return_parent_rate,
782};
783
a408e8f4
APS		 784#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \
785 LPC32XX_USB_OTG_I2C_CLOCK_ON)
786
787static int local_usb_otg_enable(struct clk *clk, int enable)
788{
789 int to = 1000;
790
791 if (enable) {
792 __raw_writel(clk->enable_mask, clk->enable_reg);
793
794 while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
795 clk->enable_mask) != clk->enable_mask) && (to > 0))
796 to--;
797 } else {
798 __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg);
799
800 while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
801 OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0))
802 to--;
803 }
804
805 if (to)
806 return 0;
807 else
808 return -1;
809}
810
811static struct clk clk_usb_otg_dev = {
812 .parent = &clk_usbpll,
813 .enable = local_usb_otg_enable,
814 .enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
815 .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
816 LPC32XX_USB_OTG_OTG_CLOCK_ON |
817 LPC32XX_USB_OTG_DEV_CLOCK_ON |
818 LPC32XX_USB_OTG_I2C_CLOCK_ON,
819 .get_rate = local_return_parent_rate,
820};
821
822static struct clk clk_usb_otg_host = {
823 .parent = &clk_usbpll,
824 .enable = local_usb_otg_enable,
825 .enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
826 .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
827 LPC32XX_USB_OTG_OTG_CLOCK_ON |
828 LPC32XX_USB_OTG_HOST_CLOCK_ON |
829 LPC32XX_USB_OTG_I2C_CLOCK_ON,
830 .get_rate = local_return_parent_rate,
831};
832
b9cc4bf6
KW		 833static int tsc_onoff_enable(struct clk *clk, int enable)
834{
835 u32 tmp;
836
837 /* Make sure 32KHz clock is the selected clock */
838 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
839 tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
840 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
841
842 if (enable == 0)
843 __raw_writel(0, clk->enable_reg);
844 else
845 __raw_writel(clk->enable_mask, clk->enable_reg);
846
847 return 0;
848}
849
850static struct clk clk_tsc = {
851 .parent = &osc_32KHz,
852 .enable = tsc_onoff_enable,
853 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
854 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
855 .get_rate = local_return_parent_rate,
856};
857
678a0222
RS		 858static int adc_onoff_enable(struct clk *clk, int enable)
859{
860 u32 tmp;
861 u32 divider;
862
863 /* Use PERIPH_CLOCK */
864 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
865 tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
866 /*
867 * Set clock divider so that we have equal to or less than
868 * 4.5MHz clock at ADC
869 */
870 divider = clk->get_rate(clk) / 4500000 + 1;
871 tmp |= divider;
872 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
873
874 /* synchronize rate of this clock w/ actual HW setting */
875 clk->rate = clk->get_rate(clk->parent) / divider;
876
877 if (enable == 0)
878 __raw_writel(0, clk->enable_reg);
879 else
880 __raw_writel(clk->enable_mask, clk->enable_reg);
881
882 return 0;
883}
884
885static struct clk clk_adc = {
886 .parent = &clk_pclk,
887 .enable = adc_onoff_enable,
888 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
889 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
890 .get_rate = local_return_parent_rate,
891};
892
b9cc4bf6
KW		 893static int mmc_onoff_enable(struct clk *clk, int enable)
894{
895 u32 tmp;
896
897 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
5df5d01d 898 ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
b0d9ef0e
RS		 899 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN |
900 LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS |
901 LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS |
902 LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS |
903 LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS);
b9cc4bf6
KW		 904
905 /* If rate is 0, disable clock */
906 if (enable != 0)
5df5d01d
RS		 907 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
908 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
b9cc4bf6
KW		 909
910 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
911
912 return 0;
913}
914
915static unsigned long mmc_get_rate(struct clk *clk)
916{
917 u32 div, rate, oldclk;
918
919 /* The MMC clock must be on when accessing an MMC register */
920 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
921 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
922 LPC32XX_CLKPWR_MS_CTRL);
923 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
924 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
925
926 /* Get the parent clock rate */
927 rate = clk->parent->get_rate(clk->parent);
928
929 /* Get the MMC controller clock divider value */
930 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
931
932 if (!div)
933 div = 1;
934
935 return rate / div;
936}
937
938static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
939{
940 unsigned long div, prate;
941
942 /* Get the parent clock rate */
943 prate = clk->parent->get_rate(clk->parent);
944
945 if (rate >= prate)
946 return prate;
947
948 div = prate / rate;
949 if (div > 0xf)
950 div = 0xf;
951
952 return prate / div;
953}
954
955static int mmc_set_rate(struct clk *clk, unsigned long rate)
956{
a0a30b6a 957 u32 tmp;
b9cc4bf6
KW		 958 unsigned long prate, div, crate = mmc_round_rate(clk, rate);
959
960 prate = clk->parent->get_rate(clk->parent);
961
962 div = prate / crate;
963
964 /* The MMC clock must be on when accessing an MMC register */
b9cc4bf6
KW		 965 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
966 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
a0a30b6a
RS		 967 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
968 LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
b9cc4bf6
KW		 969 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
970
b9cc4bf6
KW		 971 return 0;
972}
973
974static struct clk clk_mmc = {
975 .parent = &clk_armpll,
976 .set_rate = mmc_set_rate,
977 .get_rate = mmc_get_rate,
978 .round_rate = mmc_round_rate,
979 .enable = mmc_onoff_enable,
980 .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
981 .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
982};
983
984static unsigned long clcd_get_rate(struct clk *clk)
985{
986 u32 tmp, div, rate, oldclk;
987
988 /* The LCD clock must be on when accessing an LCD register */
989 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
990 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
991 LPC32XX_CLKPWR_LCDCLK_CTRL);
992 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
993 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
994
995 rate = clk->parent->get_rate(clk->parent);
996
997 /* Only supports internal clocking */
998 if (tmp & TIM2_BCD)
999 return rate;
1000
1001 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
1002 tmp = rate / (2 + div);
1003
1004 return tmp;
1005}
1006
1007static int clcd_set_rate(struct clk *clk, unsigned long rate)
1008{
1009 u32 tmp, prate, div, oldclk;
1010
1011 /* The LCD clock must be on when accessing an LCD register */
1012 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
1013 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
1014 LPC32XX_CLKPWR_LCDCLK_CTRL);
1015
1016 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
1017 prate = clk->parent->get_rate(clk->parent);
1018
1019 if (rate < prate) {
1020 /* Find closest divider */
1021 div = prate / rate;
1022 if (div >= 2) {
1023 div -= 2;
1024 tmp &= ~TIM2_BCD;
1025 }
1026
1027 tmp &= ~(0xF800001F);
1028 tmp |= (div & 0x1F);
1029 tmp |= (((div >> 5) & 0x1F) << 27);
1030 }
1031
1032 __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
1033 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
1034
1035 return 0;
1036}
1037
1038static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
1039{
1040 u32 prate, div;
1041
1042 prate = clk->parent->get_rate(clk->parent);
1043
1044 if (rate >= prate)
1045 rate = prate;
1046 else {
1047 div = prate / rate;
1048 if (div > 0x3ff)
1049 div = 0x3ff;
1050
1051 rate = prate / div;
1052 }
1053
1054 return rate;
1055}
1056
1057static struct clk clk_lcd = {
1058 .parent = &clk_hclk,
1059 .set_rate = clcd_set_rate,
1060 .get_rate = clcd_get_rate,
1061 .round_rate = clcd_round_rate,
1062 .enable = local_onoff_enable,
1063 .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
1064 .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
1065};
1066
b9cc4bf6
KW		 1067static void local_clk_disable(struct clk *clk)
1068{
b9cc4bf6
KW		 1069 /* Don't attempt to disable clock if it has no users */
1070 if (clk->usecount > 0) {
1071 clk->usecount--;
1072
1073 /* Only disable clock when it has no more users */
1074 if ((clk->usecount == 0) && (clk->enable))
1075 clk->enable(clk, 0);
1076
1077 /* Check parent clocks, they may need to be disabled too */
1078 if (clk->parent)
1079 local_clk_disable(clk->parent);
1080 }
1081}
1082
1083static int local_clk_enable(struct clk *clk)
1084{
1085 int ret = 0;
1086
1087 /* Enable parent clocks first and update use counts */
1088 if (clk->parent)
1089 ret = local_clk_enable(clk->parent);
1090
1091 if (!ret) {
1092 /* Only enable clock if it's currently disabled */
1093 if ((clk->usecount == 0) && (clk->enable))
1094 ret = clk->enable(clk, 1);
1095
1096 if (!ret)
1097 clk->usecount++;
1098 else if (clk->parent)
1099 local_clk_disable(clk->parent);
1100 }
1101
1102 return ret;
1103}
1104
1105/*
1106 * clk_enable - inform the system when the clock source should be running.
1107 */
1108int clk_enable(struct clk *clk)
1109{
1110 int ret;
b8451862 1111 unsigned long flags;
b9cc4bf6 1112
b8451862 1113 spin_lock_irqsave(&global_clkregs_lock, flags);
b9cc4bf6 1114 ret = local_clk_enable(clk);
b8451862 1115 spin_unlock_irqrestore(&global_clkregs_lock, flags);
b9cc4bf6
KW		 1116
1117 return ret;
1118}
1119EXPORT_SYMBOL(clk_enable);
1120
1121/*
1122 * clk_disable - inform the system when the clock source is no longer required
1123 */
1124void clk_disable(struct clk *clk)
1125{
b8451862
RS		 1126 unsigned long flags;
1127
1128 spin_lock_irqsave(&global_clkregs_lock, flags);
b9cc4bf6 1129 local_clk_disable(clk);
b8451862 1130 spin_unlock_irqrestore(&global_clkregs_lock, flags);
b9cc4bf6
KW		 1131}
1132EXPORT_SYMBOL(clk_disable);
1133
1134/*
1135 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1136 */
1137unsigned long clk_get_rate(struct clk *clk)
1138{
b8451862 1139 return clk->get_rate(clk);
b9cc4bf6
KW		 1140}
1141EXPORT_SYMBOL(clk_get_rate);
1142
1143/*
1144 * clk_set_rate - set the clock rate for a clock source
1145 */
1146int clk_set_rate(struct clk *clk, unsigned long rate)
1147{
1148 int ret = -EINVAL;
1149
1150 /*
1151 * Most system clocks can only be enabled or disabled, with
1152 * the actual rate set as part of the peripheral dividers
1153 * instead of high level clock control
1154 */
b8451862 1155 if (clk->set_rate)
b9cc4bf6 1156 ret = clk->set_rate(clk, rate);
b9cc4bf6
KW		 1157
1158 return ret;
1159}
1160EXPORT_SYMBOL(clk_set_rate);
1161
1162/*
1163 * clk_round_rate - adjust a rate to the exact rate a clock can provide
1164 */
1165long clk_round_rate(struct clk *clk, unsigned long rate)
1166{
b9cc4bf6
KW		 1167 if (clk->round_rate)
1168 rate = clk->round_rate(clk, rate);
1169 else
1170 rate = clk->get_rate(clk);
1171
b9cc4bf6
KW		 1172 return rate;
1173}
1174EXPORT_SYMBOL(clk_round_rate);
1175
1176/*
1177 * clk_set_parent - set the parent clock source for this clock
1178 */
1179int clk_set_parent(struct clk *clk, struct clk *parent)
1180{
1181 /* Clock re-parenting is not supported */
1182 return -EINVAL;
1183}
1184EXPORT_SYMBOL(clk_set_parent);
1185
1186/*
1187 * clk_get_parent - get the parent clock source for this clock
1188 */
1189struct clk *clk_get_parent(struct clk *clk)
1190{
1191 return clk->parent;
1192}
1193EXPORT_SYMBOL(clk_get_parent);
1194
b9cc4bf6 1195static struct clk_lookup lookups[] = {
5dfdb0a0
RS		 1196 CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
1197 CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
1198 CLKDEV_INIT(NULL, "osc_main", &osc_main),
1199 CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
1200 CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
1201 CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
1202 CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
1203 CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
1204 CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
1205 CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
1206 CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
1207 CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
1208 CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
171b0a4f
RS		 1209 CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
1210 CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
1f37a3a3 1211 CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
84cee34d 1212 CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
5dfdb0a0
RS		 1213 CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
1214 CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
1215 CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
1216 CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
171b0a4f
RS		 1217 CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
1218 CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
1219 CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
5dfdb0a0
RS		 1220 CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
1221 CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
821e7edd 1222 CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
b27f4822
RS		 1223 CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
1224 CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
171b0a4f 1225 CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
5dfdb0a0
RS		 1226 CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
1227 CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
171b0a4f
RS		 1228 CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
1229 CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
1230 CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
5dfdb0a0 1231 CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
171b0a4f 1232 CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
a408e8f4
APS		 1233 CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd),
1234 CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev),
1235 CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host),
5dfdb0a0 1236 CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
b9cc4bf6
KW		 1237};
1238
1239static int __init clk_init(void)
1240{
dd13fbd9 1241 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
b9cc4bf6
KW		 1242
1243 /*
1244 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1245 * parent clock used for the ARM PLL and is used to derive
1246 * the many system clock rates in the device.
1247 */
1248 if (clk_is_sysclk_mainosc() != 0)
1249 clk_sys.parent = &osc_main;
1250 else
1251 clk_sys.parent = &osc_pll397;
1252
1253 clk_sys.rate = clk_sys.parent->rate;
1254
1255 /* Compute the current ARM PLL and USB PLL frequencies */
1256 local_update_armpll_rate();
1257
1258 /* Compute HCLK and PCLK bus rates */
1259 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1260 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1261
1262 /*
1263 * Enable system clocks - this step is somewhat formal, as the
1264 * clocks are already running, but it does get the clock data
1265 * inline with the actual system state. Never disable these
1266 * clocks as they will only stop if the system is going to sleep.
1267 * In that case, the chip/system power management functions will
1268 * handle clock gating.
1269 */
1270 if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1271 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1272
1273 /*
1274 * Timers 0 and 1 were enabled and are being used by the high
1275 * resolution tick function prior to this driver being initialized.
1276 * Tag them now as used.
1277 */
1278 if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1279 printk(KERN_ERR "Error enabling timer tick clocks\n");
1280
1281 return 0;
1282}
1283core_initcall(clk_init);
1284
Linux kernel - Deliverables
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