[deliverable/linux.git] / arch / arm / mach-lpc32xx / common.c

/*
 * arch/arm/mach-lpc32xx/common.c
 *
 * Author: Kevin Wells <kevin.wells@nxp.com>
 *
 * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/i2c-pnx.h>
#include <linux/io.h>

#include <asm/mach/map.h>
#include <asm/system_info.h>

#include <mach/hardware.h>
#include <mach/platform.h>
#include "common.h"

/*
 * Returns the unique ID for the device
 */
void lpc32xx_get_uid(u32 devid[4])
{
	int i;

	for (i = 0; i < 4; i++)
		devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
}

/*
 * Returns SYSCLK source
 * 0 = PLL397, 1 = main oscillator
 */
int clk_is_sysclk_mainosc(void)
{
	if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
		LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
		return 1;

	return 0;
}

/*
 * System reset via the watchdog timer
 */
static void lpc32xx_watchdog_reset(void)
{
	/* Make sure WDT clocks are enabled */
	__raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
		LPC32XX_CLKPWR_TIMER_CLK_CTRL);

	/* Instant assert of RESETOUT_N with pulse length 1mS */
	__raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
	__raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
}

/*
 * Detects and returns IRAM size for the device variation
 */
#define LPC32XX_IRAM_BANK_SIZE SZ_128K
static u32 iram_size;
u32 lpc32xx_return_iram_size(void)
{
	if (iram_size == 0) {
		u32 savedval1, savedval2;
		void __iomem *iramptr1, *iramptr2;

		iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
		iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
		savedval1 = __raw_readl(iramptr1);
		savedval2 = __raw_readl(iramptr2);

		if (savedval1 == savedval2) {
			__raw_writel(savedval2 + 1, iramptr2);
			if (__raw_readl(iramptr1) == savedval2 + 1)
				iram_size = LPC32XX_IRAM_BANK_SIZE;
			else
				iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
			__raw_writel(savedval2, iramptr2);
		} else
			iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
	}

	return iram_size;
}

/*
 * Computes PLL rate from PLL register and input clock
 */
u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
{
	u32 ilfreq, p, m, n, fcco, fref, cfreq;
	int mode;

	/*
	 * PLL requirements
	 * ifreq must be >= 1MHz and <= 20MHz
	 * FCCO must be >= 156MHz and <= 320MHz
	 * FREF must be >= 1MHz and <= 27MHz
	 * Assume the passed input data is not valid
	 */

	ilfreq = ifreq;
	m = pllsetup->pll_m;
	n = pllsetup->pll_n;
	p = pllsetup->pll_p;

	mode = (pllsetup->cco_bypass_b15 << 2) |
		(pllsetup->direct_output_b14 << 1) |
	pllsetup->fdbk_div_ctrl_b13;

	switch (mode) {
	case 0x0: /* Non-integer mode */
		cfreq = (m * ilfreq) / (2 * p * n);
		fcco = (m * ilfreq) / n;
		fref = ilfreq / n;
		break;

	case 0x1: /* integer mode */
		cfreq = (m * ilfreq) / n;
		fcco = (m * ilfreq) / (n * 2 * p);
		fref = ilfreq / n;
		break;

	case 0x2:
	case 0x3: /* Direct mode */
		cfreq = (m * ilfreq) / n;
		fcco = cfreq;
		fref = ilfreq / n;
		break;

	case 0x4:
	case 0x5: /* Bypass mode */
		cfreq = ilfreq / (2 * p);
		fcco = 156000000;
		fref = 1000000;
		break;

	case 0x6:
	case 0x7: /* Direct bypass mode */
	default:
		cfreq = ilfreq;
		fcco = 156000000;
		fref = 1000000;
		break;
	}

	if (fcco < 156000000 || fcco > 320000000)
		cfreq = 0;

	if (fref < 1000000 || fref > 27000000)
		cfreq = 0;

	return (u32) cfreq;
}

u32 clk_get_pclk_div(void)
{
	return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
}

static struct map_desc lpc32xx_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
		.pfn		= __phys_to_pfn(LPC32XX_AHB0_START),
		.length		= LPC32XX_AHB0_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
		.pfn		= __phys_to_pfn(LPC32XX_AHB1_START),
		.length		= LPC32XX_AHB1_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
		.pfn		= __phys_to_pfn(LPC32XX_FABAPB_START),
		.length		= LPC32XX_FABAPB_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
		.pfn		= __phys_to_pfn(LPC32XX_IRAM_BASE),
		.length		= (LPC32XX_IRAM_BANK_SIZE * 2),
		.type		= MT_DEVICE
	},
};

void __init lpc32xx_map_io(void)
{
	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
}

void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
{
	switch (mode) {
	case REBOOT_SOFT:
	case REBOOT_HARD:
		lpc32xx_watchdog_reset();
		break;

	default:
		/* Do nothing */
		break;
	}

	/* Wait for watchdog to reset system */
	while (1)
		;
}

static int __init lpc32xx_check_uid(void)
{
	u32 uid[4];

	lpc32xx_get_uid(uid);

	printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
		uid[3], uid[2], uid[1], uid[0]);

	if (!system_serial_low && !system_serial_high) {
		system_serial_low = uid[0];
		system_serial_high = uid[1];
	}

	return 1;
}
arch_initcall(lpc32xx_check_uid);
Commit	Line	Data
fc982e1c KW	1	/*
	2	* arch/arm/mach-lpc32xx/common.c
	3	*
	4	* Author: Kevin Wells <kevin.wells@nxp.com>
	5	*
	6	* Copyright (C) 2010 NXP Semiconductors
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/irq.h>
	23	#include <linux/err.h>
	24	#include <linux/i2c.h>
	25	#include <linux/i2c-pnx.h>
	26	#include <linux/io.h>
	27
	28	#include <asm/mach/map.h>
e39942f5	29	#include <asm/system_info.h>
fc982e1c	30
fc982e1c KW	31	#include <mach/hardware.h>
	32	#include <mach/platform.h>
	33	#include "common.h"
	34
fc982e1c KW	35	/*
	36	* Returns the unique ID for the device
	37	*/
	38	void lpc32xx_get_uid(u32 devid[4])
	39	{
	40	int i;
	41
	42	for (i = 0; i < 4; i++)
	43	devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
	44	}
	45
	46	/*
	47	* Returns SYSCLK source
	48	* 0 = PLL397, 1 = main oscillator
	49	*/
	50	int clk_is_sysclk_mainosc(void)
	51	{
	52	if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
	53	LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
	54	return 1;
	55
	56	return 0;
	57	}
	58
	59	/*
	60	* System reset via the watchdog timer
	61	*/
b23fcd90	62	static void lpc32xx_watchdog_reset(void)
fc982e1c KW	63	{
	64	/* Make sure WDT clocks are enabled */
	65	__raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
	66	LPC32XX_CLKPWR_TIMER_CLK_CTRL);
	67
	68	/* Instant assert of RESETOUT_N with pulse length 1mS */
	69	__raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
	70	__raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
	71	}
	72
	73	/*
	74	* Detects and returns IRAM size for the device variation
	75	*/
	76	#define LPC32XX_IRAM_BANK_SIZE SZ_128K
	77	static u32 iram_size;
	78	u32 lpc32xx_return_iram_size(void)
	79	{
	80	if (iram_size == 0) {
	81	u32 savedval1, savedval2;
	82	void __iomem iramptr1, iramptr2;
	83
	84	iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
	85	iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
	86	savedval1 = __raw_readl(iramptr1);
	87	savedval2 = __raw_readl(iramptr2);
	88
	89	if (savedval1 == savedval2) {
	90	__raw_writel(savedval2 + 1, iramptr2);
	91	if (__raw_readl(iramptr1) == savedval2 + 1)
	92	iram_size = LPC32XX_IRAM_BANK_SIZE;
	93	else
	94	iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
	95	__raw_writel(savedval2, iramptr2);
	96	} else
	97	iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
	98	}
	99
	100	return iram_size;
	101	}
	102
	103	/*
	104	* Computes PLL rate from PLL register and input clock
	105	*/
	106	u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
	107	{
	108	u32 ilfreq, p, m, n, fcco, fref, cfreq;
	109	int mode;
	110
	111	/*
	112	* PLL requirements
	113	* ifreq must be >= 1MHz and <= 20MHz
	114	* FCCO must be >= 156MHz and <= 320MHz
	115	* FREF must be >= 1MHz and <= 27MHz
	116	* Assume the passed input data is not valid
	117	*/
	118
	119	ilfreq = ifreq;
	120	m = pllsetup->pll_m;
	121	n = pllsetup->pll_n;
	122	p = pllsetup->pll_p;
	123
	124	mode = (pllsetup->cco_bypass_b15 << 2) \|
	125	(pllsetup->direct_output_b14 << 1) \|
	126	pllsetup->fdbk_div_ctrl_b13;
127
128	switch (mode) {
129	case 0x0: /* Non-integer mode */
130	cfreq = (m * ilfreq) / (2 * p * n);
131	fcco = (m * ilfreq) / n;
132	fref = ilfreq / n;
133	break;
134
135	case 0x1: /* integer mode */
136	cfreq = (m * ilfreq) / n;
137	fcco = (m * ilfreq) / (n * 2 * p);
138	fref = ilfreq / n;
139	break;
140
141	case 0x2:
142	case 0x3: /* Direct mode */
143	cfreq = (m * ilfreq) / n;
144	fcco = cfreq;
145	fref = ilfreq / n;
146	break;
147
148	case 0x4:
149	case 0x5: /* Bypass mode */
150	cfreq = ilfreq / (2 * p);
151	fcco = 156000000;
152	fref = 1000000;
153	break;
154
155	case 0x6:
156	case 0x7: /* Direct bypass mode */
157	default:
158	cfreq = ilfreq;
159	fcco = 156000000;
160	fref = 1000000;
161	break;
162	}
163
164	if (fcco < 156000000 \|\| fcco > 320000000)
165	cfreq = 0;
166
167	if (fref < 1000000 \|\| fref > 27000000)
168	cfreq = 0;
169
170	return (u32) cfreq;
171	}
172
173	u32 clk_get_pclk_div(void)
174	{
175	return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
176	}
177
178	static struct map_desc lpc32xx_io_desc[] __initdata = {
179	{
df38b24f	180	.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
fc982e1c KW	181	.pfn = __phys_to_pfn(LPC32XX_AHB0_START),
	182	.length = LPC32XX_AHB0_SIZE,
	183	.type = MT_DEVICE
	184	},
	185	{
df38b24f	186	.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
fc982e1c KW	187	.pfn = __phys_to_pfn(LPC32XX_AHB1_START),
	188	.length = LPC32XX_AHB1_SIZE,
	189	.type = MT_DEVICE
	190	},
	191	{
df38b24f	192	.virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
fc982e1c KW	193	.pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
	194	.length = LPC32XX_FABAPB_SIZE,
	195	.type = MT_DEVICE
	196	},
	197	{
df38b24f	198	.virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
fc982e1c KW	199	.pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
	200	.length = (LPC32XX_IRAM_BANK_SIZE * 2),
	201	.type = MT_DEVICE
	202	},
	203	};
	204
	205	void __init lpc32xx_map_io(void)
	206	{
	207	iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
	208	}
b23fcd90	209
7b6d864b	210	void lpc23xx_restart(enum reboot_mode mode, const char *cmd)
b23fcd90 RK	211	{
b23fcd90 RK	212	switch (mode) {
7b6d864b RH	213	case REBOOT_SOFT:
7b6d864b RH	214	case REBOOT_HARD:
b23fcd90 RK	215	lpc32xx_watchdog_reset();
	216	break;
	217
	218	default:
	219	/* Do nothing */
	220	break;
	221	}
	222
	223	/* Wait for watchdog to reset system */
	224	while (1)
	225	;
	226	}
be20dbc8	227
e39942f5	228	static int __init lpc32xx_check_uid(void)
be20dbc8 RS	229	{
	230	u32 uid[4];
	231
	232	lpc32xx_get_uid(uid);
	233
	234	printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
	235	uid[3], uid[2], uid[1], uid[0]);
	236
e39942f5 APS	237	if (!system_serial_low && !system_serial_high) {
	238	system_serial_low = uid[0];
	239	system_serial_high = uid[1];
	240	}
	241
be20dbc8 RS	242	return 1;
be20dbc8 RS	243	}
e39942f5	244	arch_initcall(lpc32xx_check_uid);