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ARM: LPC32xx: ADC support for mach-lpc32xx
[deliverable/linux.git] / arch / arm / mach-lpc32xx / common.c
CommitLineData
fc982e1c
KW		 1/*
2 * arch/arm/mach-lpc32xx/common.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/err.h>
24#include <linux/i2c.h>
25#include <linux/i2c-pnx.h>
26#include <linux/io.h>
27
28#include <asm/mach/map.h>
29
30#include <mach/i2c.h>
31#include <mach/hardware.h>
32#include <mach/platform.h>
33#include "common.h"
34
35/*
36 * Watchdog timer
37 */
38static struct resource watchdog_resources[] = {
39 [0] = {
40 .start = LPC32XX_WDTIM_BASE,
41 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
42 .flags = IORESOURCE_MEM,
43 },
44};
45
46struct platform_device lpc32xx_watchdog_device = {
47 .name = "pnx4008-watchdog",
48 .id = -1,
49 .num_resources = ARRAY_SIZE(watchdog_resources),
50 .resource = watchdog_resources,
51};
52
53/*
54 * I2C busses
55 */
56static struct i2c_pnx_data i2c0_data = {
57 .name = I2C_CHIP_NAME "1",
58 .base = LPC32XX_I2C1_BASE,
59 .irq = IRQ_LPC32XX_I2C_1,
60};
61
62static struct i2c_pnx_data i2c1_data = {
63 .name = I2C_CHIP_NAME "2",
64 .base = LPC32XX_I2C2_BASE,
65 .irq = IRQ_LPC32XX_I2C_2,
66};
67
68static struct i2c_pnx_data i2c2_data = {
69 .name = "USB-I2C",
70 .base = LPC32XX_OTG_I2C_BASE,
71 .irq = IRQ_LPC32XX_USB_I2C,
72};
73
74struct platform_device lpc32xx_i2c0_device = {
75 .name = "pnx-i2c",
76 .id = 0,
77 .dev = {
78 .platform_data = &i2c0_data,
79 },
80};
81
82struct platform_device lpc32xx_i2c1_device = {
83 .name = "pnx-i2c",
84 .id = 1,
85 .dev = {
86 .platform_data = &i2c1_data,
87 },
88};
89
90struct platform_device lpc32xx_i2c2_device = {
91 .name = "pnx-i2c",
92 .id = 2,
93 .dev = {
94 .platform_data = &i2c2_data,
95 },
96};
97
7db2b377
WS		 98/* TSC (Touch Screen Controller) */
99
100static struct resource lpc32xx_tsc_resources[] = {
101 {
102 .start = LPC32XX_ADC_BASE,
103 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
104 .flags = IORESOURCE_MEM,
105 }, {
106 .start = IRQ_LPC32XX_TS_IRQ,
107 .end = IRQ_LPC32XX_TS_IRQ,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112struct platform_device lpc32xx_tsc_device = {
113 .name = "ts-lpc32xx",
114 .id = -1,
115 .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
116 .resource = lpc32xx_tsc_resources,
117};
118
1c72f9ea
WS		 119/* RTC */
120
121static struct resource lpc32xx_rtc_resources[] = {
122 {
123 .start = LPC32XX_RTC_BASE,
124 .end = LPC32XX_RTC_BASE + SZ_4K - 1,
125 .flags = IORESOURCE_MEM,
126 },{
127 .start = IRQ_LPC32XX_RTC,
128 .end = IRQ_LPC32XX_RTC,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133struct platform_device lpc32xx_rtc_device = {
134 .name = "rtc-lpc32xx",
135 .id = -1,
136 .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
137 .resource = lpc32xx_rtc_resources,
138};
139
678a0222
RS		 140/*
141 * ADC support
142 */
143static struct resource adc_resources[] = {
144 {
145 .start = LPC32XX_ADC_BASE,
146 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
147 .flags = IORESOURCE_MEM,
148 }, {
149 .start = IRQ_LPC32XX_TS_IRQ,
150 .end = IRQ_LPC32XX_TS_IRQ,
151 .flags = IORESOURCE_IRQ,
152 },
153};
154
155struct platform_device lpc32xx_adc_device = {
156 .name = "lpc32xx-adc",
157 .id = -1,
158 .num_resources = ARRAY_SIZE(adc_resources),
159 .resource = adc_resources,
160};
161
fc982e1c
KW		 162/*
163 * Returns the unique ID for the device
164 */
165void lpc32xx_get_uid(u32 devid[4])
166{
167 int i;
168
169 for (i = 0; i < 4; i++)
170 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
171}
172
173/*
174 * Returns SYSCLK source
175 * 0 = PLL397, 1 = main oscillator
176 */
177int clk_is_sysclk_mainosc(void)
178{
179 if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
180 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
181 return 1;
182
183 return 0;
184}
185
186/*
187 * System reset via the watchdog timer
188 */
b23fcd90 189static void lpc32xx_watchdog_reset(void)
fc982e1c
KW		 190{
191 /* Make sure WDT clocks are enabled */
192 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
193 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
194
195 /* Instant assert of RESETOUT_N with pulse length 1mS */
196 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
197 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
198}
199
200/*
201 * Detects and returns IRAM size for the device variation
202 */
203#define LPC32XX_IRAM_BANK_SIZE SZ_128K
204static u32 iram_size;
205u32 lpc32xx_return_iram_size(void)
206{
207 if (iram_size == 0) {
208 u32 savedval1, savedval2;
209 void __iomem *iramptr1, *iramptr2;
210
211 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
212 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
213 savedval1 = __raw_readl(iramptr1);
214 savedval2 = __raw_readl(iramptr2);
215
216 if (savedval1 == savedval2) {
217 __raw_writel(savedval2 + 1, iramptr2);
218 if (__raw_readl(iramptr1) == savedval2 + 1)
219 iram_size = LPC32XX_IRAM_BANK_SIZE;
220 else
221 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
222 __raw_writel(savedval2, iramptr2);
223 } else
224 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
225 }
226
227 return iram_size;
228}
229
230/*
231 * Computes PLL rate from PLL register and input clock
232 */
233u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
234{
235 u32 ilfreq, p, m, n, fcco, fref, cfreq;
236 int mode;
237
238 /*
239 * PLL requirements
240 * ifreq must be >= 1MHz and <= 20MHz
241 * FCCO must be >= 156MHz and <= 320MHz
242 * FREF must be >= 1MHz and <= 27MHz
243 * Assume the passed input data is not valid
244 */
245
246 ilfreq = ifreq;
247 m = pllsetup->pll_m;
248 n = pllsetup->pll_n;
249 p = pllsetup->pll_p;
250
251 mode = (pllsetup->cco_bypass_b15 << 2) |
252 (pllsetup->direct_output_b14 << 1) |
253 pllsetup->fdbk_div_ctrl_b13;
254
255 switch (mode) {
256 case 0x0: /* Non-integer mode */
257 cfreq = (m * ilfreq) / (2 * p * n);
258 fcco = (m * ilfreq) / n;
259 fref = ilfreq / n;
260 break;
261
262 case 0x1: /* integer mode */
263 cfreq = (m * ilfreq) / n;
264 fcco = (m * ilfreq) / (n * 2 * p);
265 fref = ilfreq / n;
266 break;
267
268 case 0x2:
269 case 0x3: /* Direct mode */
270 cfreq = (m * ilfreq) / n;
271 fcco = cfreq;
272 fref = ilfreq / n;
273 break;
274
275 case 0x4:
276 case 0x5: /* Bypass mode */
277 cfreq = ilfreq / (2 * p);
278 fcco = 156000000;
279 fref = 1000000;
280 break;
281
282 case 0x6:
283 case 0x7: /* Direct bypass mode */
284 default:
285 cfreq = ilfreq;
286 fcco = 156000000;
287 fref = 1000000;
288 break;
289 }
290
291 if (fcco < 156000000 || fcco > 320000000)
292 cfreq = 0;
293
294 if (fref < 1000000 || fref > 27000000)
295 cfreq = 0;
296
297 return (u32) cfreq;
298}
299
300u32 clk_get_pclk_div(void)
301{
302 return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
303}
304
305static struct map_desc lpc32xx_io_desc[] __initdata = {
306 {
307 .virtual = IO_ADDRESS(LPC32XX_AHB0_START),
308 .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
309 .length = LPC32XX_AHB0_SIZE,
310 .type = MT_DEVICE
311 },
312 {
313 .virtual = IO_ADDRESS(LPC32XX_AHB1_START),
314 .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
315 .length = LPC32XX_AHB1_SIZE,
316 .type = MT_DEVICE
317 },
318 {
319 .virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
320 .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
321 .length = LPC32XX_FABAPB_SIZE,
322 .type = MT_DEVICE
323 },
324 {
325 .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
326 .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
327 .length = (LPC32XX_IRAM_BANK_SIZE * 2),
328 .type = MT_DEVICE
329 },
330};
331
332void __init lpc32xx_map_io(void)
333{
334 iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
335}
b23fcd90
RK		 336
337void lpc23xx_restart(char mode, const char *cmd)
338{
339 switch (mode) {
340 case 's':
341 case 'h':
b23fcd90
RK		 342 lpc32xx_watchdog_reset();
343 break;
344
345 default:
346 /* Do nothing */
347 break;
348 }
349
350 /* Wait for watchdog to reset system */
351 while (1)
352 ;
353}
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