Commit | Line | Data |
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49cbe786 EM |
1 | /* |
2 | * linux/arch/arm/mach-mmp/pxa168.c | |
3 | * | |
4 | * Code specific to PXA168 | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/clk.h> | |
16 | ||
17 | #include <asm/mach/time.h> | |
18 | #include <mach/addr-map.h> | |
19 | #include <mach/cputype.h> | |
20 | #include <mach/regs-apbc.h> | |
21 | #include <mach/irqs.h> | |
22 | #include <mach/dma.h> | |
23 | #include <mach/devices.h> | |
24 | ||
25 | #include "common.h" | |
26 | #include "clock.h" | |
27 | ||
28 | void __init pxa168_init_irq(void) | |
29 | { | |
30 | icu_init_irq(); | |
31 | } | |
32 | ||
33 | /* APB peripheral clocks */ | |
34 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); | |
35 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); | |
36 | ||
37 | /* device and clock bindings */ | |
38 | static struct clk_lookup pxa168_clkregs[] = { | |
39 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | |
40 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | |
41 | }; | |
42 | ||
43 | static int __init pxa168_init(void) | |
44 | { | |
45 | if (cpu_is_pxa168()) { | |
46 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); | |
47 | clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); | |
48 | } | |
49 | ||
50 | return 0; | |
51 | } | |
52 | postcore_initcall(pxa168_init); | |
53 | ||
54 | /* system timer - clock enabled, 3.25MHz */ | |
55 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | |
56 | ||
57 | static void __init pxa168_timer_init(void) | |
58 | { | |
59 | /* this is early, we have to initialize the CCU registers by | |
60 | * ourselves instead of using clk_* API. Clock rate is defined | |
61 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running | |
62 | */ | |
63 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); | |
64 | ||
65 | /* 3.25MHz, bus/functional clock enabled, release reset */ | |
66 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); | |
67 | ||
68 | timer_init(IRQ_PXA168_TIMER1); | |
69 | } | |
70 | ||
71 | struct sys_timer pxa168_timer = { | |
72 | .init = pxa168_timer_init, | |
73 | }; | |
74 | ||
75 | /* on-chip devices */ | |
76 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); | |
77 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); |