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14c6b5e7 EM |
1 | /* |
2 | * linux/arch/arm/mach-mmp/pxa910.c | |
3 | * | |
4 | * Code specific to PXA910 | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
990f2f22 | 10 | #include <linux/clk/mmp.h> |
14c6b5e7 EM |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/io.h> | |
0f102b6c HZ |
16 | #include <linux/irq.h> |
17 | #include <linux/irqchip/mmp.h> | |
157d2644 | 18 | #include <linux/platform_device.h> |
14c6b5e7 | 19 | |
a03d8b1e | 20 | #include <asm/hardware/cache-tauros2.h> |
14c6b5e7 | 21 | #include <asm/mach/time.h> |
b501fd7b AB |
22 | #include "addr-map.h" |
23 | #include "regs-apbc.h" | |
24 | #include "cputype.h" | |
25 | #include "irqs.h" | |
26 | #include "mfp.h" | |
27 | #include "devices.h" | |
28 | #include "pm-pxa910.h" | |
29 | #include "pxa910.h" | |
14c6b5e7 EM |
30 | |
31 | #include "common.h" | |
14c6b5e7 EM |
32 | |
33 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | |
34 | ||
35 | static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = | |
36 | { | |
37 | MFP_ADDR_X(GPIO0, GPIO54, 0xdc), | |
38 | MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), | |
39 | MFP_ADDR_X(GPIO100, GPIO109, 0x238), | |
40 | ||
41 | MFP_ADDR(GPIO123, 0xcc), | |
42 | MFP_ADDR(GPIO124, 0xd0), | |
43 | ||
44 | MFP_ADDR(DF_IO0, 0x40), | |
45 | MFP_ADDR(DF_IO1, 0x3c), | |
46 | MFP_ADDR(DF_IO2, 0x38), | |
47 | MFP_ADDR(DF_IO3, 0x34), | |
48 | MFP_ADDR(DF_IO4, 0x30), | |
49 | MFP_ADDR(DF_IO5, 0x2c), | |
50 | MFP_ADDR(DF_IO6, 0x28), | |
51 | MFP_ADDR(DF_IO7, 0x24), | |
52 | MFP_ADDR(DF_IO8, 0x20), | |
53 | MFP_ADDR(DF_IO9, 0x1c), | |
54 | MFP_ADDR(DF_IO10, 0x18), | |
55 | MFP_ADDR(DF_IO11, 0x14), | |
56 | MFP_ADDR(DF_IO12, 0x10), | |
57 | MFP_ADDR(DF_IO13, 0xc), | |
58 | MFP_ADDR(DF_IO14, 0x8), | |
59 | MFP_ADDR(DF_IO15, 0x4), | |
60 | ||
61 | MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), | |
62 | MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), | |
63 | MFP_ADDR(SM_nCS0, 0x4c), | |
64 | MFP_ADDR(SM_nCS1, 0x50), | |
65 | MFP_ADDR(DF_WEn, 0x54), | |
66 | MFP_ADDR(DF_REn, 0x58), | |
67 | MFP_ADDR(DF_CLE_SM_OEn, 0x5c), | |
68 | MFP_ADDR(DF_ALE_SM_WEn, 0x60), | |
69 | MFP_ADDR(SM_SCLK, 0x64), | |
70 | MFP_ADDR(DF_RDY0, 0x68), | |
71 | MFP_ADDR(SM_BE0, 0x6c), | |
72 | MFP_ADDR(SM_BE1, 0x70), | |
73 | MFP_ADDR(SM_ADV, 0x74), | |
74 | MFP_ADDR(DF_RDY1, 0x78), | |
75 | MFP_ADDR(SM_ADVMUX, 0x7c), | |
76 | MFP_ADDR(SM_RDY, 0x80), | |
77 | ||
78 | MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), | |
79 | ||
80 | MFP_ADDR_END, | |
81 | }; | |
82 | ||
14c6b5e7 EM |
83 | void __init pxa910_init_irq(void) |
84 | { | |
85 | icu_init_irq(); | |
0f102b6c HZ |
86 | #ifdef CONFIG_PM |
87 | icu_irq_chip.irq_set_wake = pxa910_set_wake; | |
88 | #endif | |
14c6b5e7 EM |
89 | } |
90 | ||
14c6b5e7 EM |
91 | static int __init pxa910_init(void) |
92 | { | |
93 | if (cpu_is_pxa910()) { | |
a03d8b1e HZ |
94 | #ifdef CONFIG_CACHE_TAUROS2 |
95 | tauros2_init(0); | |
96 | #endif | |
14c6b5e7 EM |
97 | mfp_init_base(MFPR_VIRT_BASE); |
98 | mfp_init_addr(pxa910_mfp_addr_map); | |
990f2f22 AB |
99 | pxa910_clk_init(APB_PHYS_BASE + 0x50000, |
100 | AXI_PHYS_BASE + 0x82800, | |
101 | APB_PHYS_BASE + 0x15000, | |
102 | APB_PHYS_BASE + 0x3b000); | |
14c6b5e7 EM |
103 | } |
104 | ||
105 | return 0; | |
106 | } | |
107 | postcore_initcall(pxa910_init); | |
108 | ||
109 | /* system timer - clock enabled, 3.25MHz */ | |
110 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | |
9e73d698 | 111 | #define APBC_TIMERS APBC_REG(0x34) |
14c6b5e7 | 112 | |
6bb27d73 | 113 | void __init pxa910_timer_init(void) |
14c6b5e7 EM |
114 | { |
115 | /* reset and configure */ | |
9e73d698 CX |
116 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); |
117 | __raw_writel(TIMER_CLK_RST, APBC_TIMERS); | |
14c6b5e7 EM |
118 | |
119 | timer_init(IRQ_PXA910_AP1_TIMER1); | |
120 | } | |
121 | ||
14c6b5e7 EM |
122 | /* on-chip devices */ |
123 | ||
124 | /* NOTE: there are totally 3 UARTs on PXA910: | |
125 | * | |
126 | * UART1 - Slow UART (can be used both by AP and CP) | |
127 | * UART2/3 - Fast UART | |
128 | * | |
129 | * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, | |
130 | * they are re-ordered as: | |
131 | * | |
132 | * pxa910_device_uart1 - UART2 as FFUART | |
133 | * pxa910_device_uart2 - UART3 as BTUART | |
134 | * | |
135 | * UART1 is not used by AP for the moment. | |
136 | */ | |
137 | PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); | |
138 | PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); | |
1a77920e EM |
139 | PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); |
140 | PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); | |
a27ba768 EM |
141 | PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10); |
142 | PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); | |
143 | PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); | |
144 | PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); | |
a0f266c1 | 145 | PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); |
333893cd ZZ |
146 | PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec); |
147 | PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0); | |
148 | PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0); | |
157d2644 HZ |
149 | |
150 | struct resource pxa910_resource_gpio[] = { | |
151 | { | |
152 | .start = 0xd4019000, | |
153 | .end = 0xd4019fff, | |
154 | .flags = IORESOURCE_MEM, | |
155 | }, { | |
156 | .start = IRQ_PXA910_AP_GPIO, | |
157 | .end = IRQ_PXA910_AP_GPIO, | |
93413c36 | 158 | .name = "gpio_mux", |
157d2644 HZ |
159 | .flags = IORESOURCE_IRQ, |
160 | }, | |
161 | }; | |
162 | ||
163 | struct platform_device pxa910_device_gpio = { | |
2cab0292 | 164 | .name = "mmp-gpio", |
157d2644 HZ |
165 | .id = -1, |
166 | .num_resources = ARRAY_SIZE(pxa910_resource_gpio), | |
167 | .resource = pxa910_resource_gpio, | |
168 | }; | |
4128e275 HZ |
169 | |
170 | static struct resource pxa910_resource_rtc[] = { | |
171 | { | |
172 | .start = 0xd4010000, | |
173 | .end = 0xd401003f, | |
174 | .flags = IORESOURCE_MEM, | |
175 | }, { | |
176 | .start = IRQ_PXA910_RTC_INT, | |
177 | .end = IRQ_PXA910_RTC_INT, | |
178 | .name = "rtc 1Hz", | |
179 | .flags = IORESOURCE_IRQ, | |
180 | }, { | |
181 | .start = IRQ_PXA910_RTC_ALARM, | |
182 | .end = IRQ_PXA910_RTC_ALARM, | |
183 | .name = "rtc alarm", | |
184 | .flags = IORESOURCE_IRQ, | |
185 | }, | |
186 | }; | |
187 | ||
188 | struct platform_device pxa910_device_rtc = { | |
189 | .name = "sa1100-rtc", | |
190 | .id = -1, | |
191 | .num_resources = ARRAY_SIZE(pxa910_resource_rtc), | |
192 | .resource = pxa910_resource_rtc, | |
193 | }; |