[deliverable/linux.git] / arch / arm / mach-mmp / pxa910.c

/*
 *  linux/arch/arm/mach-mmp/pxa910.c
 *
 *  Code specific to PXA910
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/mmp.h>
#include <linux/platform_device.h>

#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/time.h>
#include <mach/addr-map.h>
#include <mach/regs-apbc.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/dma.h>
#include <mach/mfp.h>
#include <mach/devices.h>
#include <mach/pm-pxa910.h>
#include <mach/pxa910.h>

#include "common.h"

#define MFPR_VIRT_BASE	(APB_VIRT_BASE + 0x1e000)

static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
{
	MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
	MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
	MFP_ADDR_X(GPIO100, GPIO109, 0x238),

	MFP_ADDR(GPIO123, 0xcc),
	MFP_ADDR(GPIO124, 0xd0),

	MFP_ADDR(DF_IO0, 0x40),
	MFP_ADDR(DF_IO1, 0x3c),
	MFP_ADDR(DF_IO2, 0x38),
	MFP_ADDR(DF_IO3, 0x34),
	MFP_ADDR(DF_IO4, 0x30),
	MFP_ADDR(DF_IO5, 0x2c),
	MFP_ADDR(DF_IO6, 0x28),
	MFP_ADDR(DF_IO7, 0x24),
	MFP_ADDR(DF_IO8, 0x20),
	MFP_ADDR(DF_IO9, 0x1c),
	MFP_ADDR(DF_IO10, 0x18),
	MFP_ADDR(DF_IO11, 0x14),
	MFP_ADDR(DF_IO12, 0x10),
	MFP_ADDR(DF_IO13, 0xc),
	MFP_ADDR(DF_IO14, 0x8),
	MFP_ADDR(DF_IO15, 0x4),

	MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
	MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
	MFP_ADDR(SM_nCS0, 0x4c),
	MFP_ADDR(SM_nCS1, 0x50),
	MFP_ADDR(DF_WEn, 0x54),
	MFP_ADDR(DF_REn, 0x58),
	MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
	MFP_ADDR(DF_ALE_SM_WEn, 0x60),
	MFP_ADDR(SM_SCLK, 0x64),
	MFP_ADDR(DF_RDY0, 0x68),
	MFP_ADDR(SM_BE0, 0x6c),
	MFP_ADDR(SM_BE1, 0x70),
	MFP_ADDR(SM_ADV, 0x74),
	MFP_ADDR(DF_RDY1, 0x78),
	MFP_ADDR(SM_ADVMUX, 0x7c),
	MFP_ADDR(SM_RDY, 0x80),

	MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),

	MFP_ADDR_END,
};

void __init pxa910_init_irq(void)
{
	icu_init_irq();
#ifdef CONFIG_PM
	icu_irq_chip.irq_set_wake = pxa910_set_wake;
#endif
}

static int __init pxa910_init(void)
{
	if (cpu_is_pxa910()) {
#ifdef CONFIG_CACHE_TAUROS2
		tauros2_init(0);
#endif
		mfp_init_base(MFPR_VIRT_BASE);
		mfp_init_addr(pxa910_mfp_addr_map);
		pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
		pxa910_clk_init();
	}

	return 0;
}
postcore_initcall(pxa910_init);

/* system timer - clock enabled, 3.25MHz */
#define TIMER_CLK_RST	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
#define APBC_TIMERS	APBC_REG(0x34)

void __init pxa910_timer_init(void)
{
	/* reset and configure */
	__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
	__raw_writel(TIMER_CLK_RST, APBC_TIMERS);

	timer_init(IRQ_PXA910_AP1_TIMER1);
}

/* on-chip devices */

/* NOTE: there are totally 3 UARTs on PXA910:
 *
 *   UART1   - Slow UART (can be used both by AP and CP)
 *   UART2/3 - Fast UART
 *
 * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
 * they are re-ordered as:
 *
 *   pxa910_device_uart1 - UART2 as FFUART
 *   pxa910_device_uart2 - UART3 as BTUART
 *
 * UART1 is not used by AP for the moment.
 */
PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);

struct resource pxa910_resource_gpio[] = {
	{
		.start	= 0xd4019000,
		.end	= 0xd4019fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_PXA910_AP_GPIO,
		.end	= IRQ_PXA910_AP_GPIO,
		.name	= "gpio_mux",
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa910_device_gpio = {
	.name		= "mmp-gpio",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(pxa910_resource_gpio),
	.resource	= pxa910_resource_gpio,
};

static struct resource pxa910_resource_rtc[] = {
	{
		.start	= 0xd4010000,
		.end	= 0xd401003f,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_PXA910_RTC_INT,
		.end	= IRQ_PXA910_RTC_INT,
		.name	= "rtc 1Hz",
		.flags	= IORESOURCE_IRQ,
	}, {
		.start	= IRQ_PXA910_RTC_ALARM,
		.end	= IRQ_PXA910_RTC_ALARM,
		.name	= "rtc alarm",
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa910_device_rtc = {
	.name		= "sa1100-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(pxa910_resource_rtc),
	.resource	= pxa910_resource_rtc,
};
Commit	Line	Data
14c6b5e7 EM	1	/*
	2	* linux/arch/arm/mach-mmp/pxa910.c
	3	*
	4	* Code specific to PXA910
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
14c6b5e7 EM	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
	14	#include <linux/io.h>
0f102b6c HZ	15	#include <linux/irq.h>
0f102b6c HZ	16	#include <linux/irqchip/mmp.h>
157d2644	17	#include <linux/platform_device.h>
14c6b5e7	18
a03d8b1e	19	#include <asm/hardware/cache-tauros2.h>
14c6b5e7 EM	20	#include <asm/mach/time.h>
	21	#include <mach/addr-map.h>
	22	#include <mach/regs-apbc.h>
14c6b5e7 EM	23	#include <mach/cputype.h>
14c6b5e7 EM	24	#include <mach/irqs.h>
14c6b5e7 EM	25	#include <mach/dma.h>
	26	#include <mach/mfp.h>
	27	#include <mach/devices.h>
0f102b6c	28	#include <mach/pm-pxa910.h>
c052d13c	29	#include <mach/pxa910.h>
14c6b5e7 EM	30
14c6b5e7 EM	31	#include "common.h"
14c6b5e7 EM	32
	33	#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
	34
	35	static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
	36	{
	37	MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
	38	MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
	39	MFP_ADDR_X(GPIO100, GPIO109, 0x238),
	40
	41	MFP_ADDR(GPIO123, 0xcc),
	42	MFP_ADDR(GPIO124, 0xd0),
	43
	44	MFP_ADDR(DF_IO0, 0x40),
	45	MFP_ADDR(DF_IO1, 0x3c),
	46	MFP_ADDR(DF_IO2, 0x38),
	47	MFP_ADDR(DF_IO3, 0x34),
	48	MFP_ADDR(DF_IO4, 0x30),
	49	MFP_ADDR(DF_IO5, 0x2c),
	50	MFP_ADDR(DF_IO6, 0x28),
	51	MFP_ADDR(DF_IO7, 0x24),
	52	MFP_ADDR(DF_IO8, 0x20),
	53	MFP_ADDR(DF_IO9, 0x1c),
	54	MFP_ADDR(DF_IO10, 0x18),
	55	MFP_ADDR(DF_IO11, 0x14),
	56	MFP_ADDR(DF_IO12, 0x10),
	57	MFP_ADDR(DF_IO13, 0xc),
	58	MFP_ADDR(DF_IO14, 0x8),
	59	MFP_ADDR(DF_IO15, 0x4),
	60
	61	MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
	62	MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
	63	MFP_ADDR(SM_nCS0, 0x4c),
	64	MFP_ADDR(SM_nCS1, 0x50),
	65	MFP_ADDR(DF_WEn, 0x54),
	66	MFP_ADDR(DF_REn, 0x58),
	67	MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
	68	MFP_ADDR(DF_ALE_SM_WEn, 0x60),
	69	MFP_ADDR(SM_SCLK, 0x64),
	70	MFP_ADDR(DF_RDY0, 0x68),
	71	MFP_ADDR(SM_BE0, 0x6c),
	72	MFP_ADDR(SM_BE1, 0x70),
	73	MFP_ADDR(SM_ADV, 0x74),
	74	MFP_ADDR(DF_RDY1, 0x78),
	75	MFP_ADDR(SM_ADVMUX, 0x7c),
	76	MFP_ADDR(SM_RDY, 0x80),
	77
	78	MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
	79
	80	MFP_ADDR_END,
	81	};
	82
14c6b5e7 EM	83	void __init pxa910_init_irq(void)
	84	{
	85	icu_init_irq();
0f102b6c HZ	86	#ifdef CONFIG_PM
	87	icu_irq_chip.irq_set_wake = pxa910_set_wake;
	88	#endif
14c6b5e7 EM	89	}
14c6b5e7 EM	90
14c6b5e7 EM	91	static int __init pxa910_init(void)
	92	{
	93	if (cpu_is_pxa910()) {
a03d8b1e HZ	94	#ifdef CONFIG_CACHE_TAUROS2
	95	tauros2_init(0);
	96	#endif
14c6b5e7 EM	97	mfp_init_base(MFPR_VIRT_BASE);
	98	mfp_init_addr(pxa910_mfp_addr_map);
	99	pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
9e73d698	100	pxa910_clk_init();
14c6b5e7 EM	101	}
	102
	103	return 0;
	104	}
	105	postcore_initcall(pxa910_init);
	106
	107	/* system timer - clock enabled, 3.25MHz */
	108	#define TIMER_CLK_RST (APBC_APBCLK \| APBC_FNCLK \| APBC_FNCLKSEL(3))
9e73d698	109	#define APBC_TIMERS APBC_REG(0x34)
14c6b5e7	110
6bb27d73	111	void __init pxa910_timer_init(void)
14c6b5e7 EM	112	{
14c6b5e7 EM	113	/* reset and configure */
9e73d698 CX	114	__raw_writel(APBC_APBCLK \| APBC_RST, APBC_TIMERS);
9e73d698 CX	115	__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
14c6b5e7 EM	116
	117	timer_init(IRQ_PXA910_AP1_TIMER1);
	118	}
	119
14c6b5e7 EM	120	/* on-chip devices */
	121
	122	/* NOTE: there are totally 3 UARTs on PXA910:
	123	*
	124	* UART1 - Slow UART (can be used both by AP and CP)
	125	* UART2/3 - Fast UART
	126	*
	127	* To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
	128	* they are re-ordered as:
	129	*
	130	* pxa910_device_uart1 - UART2 as FFUART
	131	* pxa910_device_uart2 - UART3 as BTUART
	132	*
	133	* UART1 is not used by AP for the moment.
	134	*/
	135	PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
	136	PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
1a77920e EM	137	PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
1a77920e EM	138	PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
a27ba768 EM	139	PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
	140	PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
	141	PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
	142	PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
a0f266c1	143	PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
333893cd ZZ	144	PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec);
	145	PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0);
	146	PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0);
157d2644 HZ	147
	148	struct resource pxa910_resource_gpio[] = {
	149	{
	150	.start = 0xd4019000,
	151	.end = 0xd4019fff,
	152	.flags = IORESOURCE_MEM,
	153	}, {
	154	.start = IRQ_PXA910_AP_GPIO,
	155	.end = IRQ_PXA910_AP_GPIO,
93413c36	156	.name = "gpio_mux",
157d2644 HZ	157	.flags = IORESOURCE_IRQ,
	158	},
	159	};
	160
	161	struct platform_device pxa910_device_gpio = {
2cab0292	162	.name = "mmp-gpio",
157d2644 HZ	163	.id = -1,
	164	.num_resources = ARRAY_SIZE(pxa910_resource_gpio),
	165	.resource = pxa910_resource_gpio,
	166	};
4128e275 HZ	167
	168	static struct resource pxa910_resource_rtc[] = {
	169	{
	170	.start = 0xd4010000,
	171	.end = 0xd401003f,
	172	.flags = IORESOURCE_MEM,
	173	}, {
	174	.start = IRQ_PXA910_RTC_INT,
	175	.end = IRQ_PXA910_RTC_INT,
	176	.name = "rtc 1Hz",
	177	.flags = IORESOURCE_IRQ,
	178	}, {
	179	.start = IRQ_PXA910_RTC_ALARM,
	180	.end = IRQ_PXA910_RTC_ALARM,
	181	.name = "rtc alarm",
	182	.flags = IORESOURCE_IRQ,
	183	},
	184	};
	185
	186	struct platform_device pxa910_device_rtc = {
	187	.name = "sa1100-rtc",
	188	.id = -1,
	189	.num_resources = ARRAY_SIZE(pxa910_resource_rtc),
	190	.resource = pxa910_resource_rtc,
	191	};