Commit | Line | Data |
---|---|---|
49cbe786 EM |
1 | /* |
2 | * linux/arch/arm/mach-mmp/time.c | |
3 | * | |
4 | * Support for clocksource and clockevents | |
5 | * | |
6 | * Copyright (C) 2008 Marvell International Ltd. | |
7 | * All rights reserved. | |
8 | * | |
9 | * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> | |
10 | * 2008-10-08: Bin Yang <bin.yang@marvell.com> | |
11 | * | |
25985edc | 12 | * The timers module actually includes three timers, each timer with up to |
49cbe786 EM |
13 | * three match comparators. Timer #0 is used here in free-running mode as |
14 | * the clock source, and match comparator #1 used as clock event device. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/clockchips.h> | |
25 | ||
26 | #include <linux/io.h> | |
27 | #include <linux/irq.h> | |
c68ef2b5 HZ |
28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
38ff87f7 | 31 | #include <linux/sched_clock.h> |
49cbe786 EM |
32 | |
33 | #include <mach/addr-map.h> | |
34 | #include <mach/regs-timers.h> | |
2f7e8fae | 35 | #include <mach/regs-apbc.h> |
49cbe786 | 36 | #include <mach/irqs.h> |
2f7e8fae HZ |
37 | #include <mach/cputype.h> |
38 | #include <asm/mach/time.h> | |
49cbe786 EM |
39 | |
40 | #include "clock.h" | |
41 | ||
ea158119 UKK |
42 | #ifdef CONFIG_CPU_MMP2 |
43 | #define MMP_CLOCK_FREQ 6500000 | |
44 | #else | |
45 | #define MMP_CLOCK_FREQ 3250000 | |
46 | #endif | |
47 | ||
49cbe786 EM |
48 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE |
49 | ||
50 | #define MAX_DELTA (0xfffffffe) | |
51 | #define MIN_DELTA (16) | |
52 | ||
c68ef2b5 HZ |
53 | static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; |
54 | ||
49cbe786 EM |
55 | /* |
56 | * FIXME: the timer needs some delay to stablize the counter capture | |
57 | */ | |
58 | static inline uint32_t timer_read(void) | |
59 | { | |
60 | int delay = 100; | |
61 | ||
c68ef2b5 | 62 | __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); |
49cbe786 EM |
63 | |
64 | while (delay--) | |
65 | cpu_relax(); | |
66 | ||
c68ef2b5 | 67 | return __raw_readl(mmp_timer_base + TMR_CVWR(1)); |
49cbe786 EM |
68 | } |
69 | ||
e5c0228d | 70 | static u64 notrace mmp_read_sched_clock(void) |
49cbe786 | 71 | { |
2f0778af | 72 | return timer_read(); |
49cbe786 EM |
73 | } |
74 | ||
75 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | |
76 | { | |
77 | struct clock_event_device *c = dev_id; | |
78 | ||
af9dafb1 LB |
79 | /* |
80 | * Clear pending interrupt status. | |
81 | */ | |
c68ef2b5 | 82 | __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); |
af9dafb1 LB |
83 | |
84 | /* | |
85 | * Disable timer 0. | |
86 | */ | |
c68ef2b5 | 87 | __raw_writel(0x02, mmp_timer_base + TMR_CER); |
af9dafb1 | 88 | |
49cbe786 | 89 | c->event_handler(c); |
af9dafb1 | 90 | |
49cbe786 EM |
91 | return IRQ_HANDLED; |
92 | } | |
93 | ||
94 | static int timer_set_next_event(unsigned long delta, | |
95 | struct clock_event_device *dev) | |
96 | { | |
af9dafb1 | 97 | unsigned long flags; |
49cbe786 EM |
98 | |
99 | local_irq_save(flags); | |
100 | ||
af9dafb1 LB |
101 | /* |
102 | * Disable timer 0. | |
103 | */ | |
c68ef2b5 | 104 | __raw_writel(0x02, mmp_timer_base + TMR_CER); |
af9dafb1 LB |
105 | |
106 | /* | |
107 | * Clear and enable timer match 0 interrupt. | |
108 | */ | |
c68ef2b5 HZ |
109 | __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); |
110 | __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); | |
49cbe786 | 111 | |
af9dafb1 LB |
112 | /* |
113 | * Setup new clockevent timer value. | |
114 | */ | |
c68ef2b5 | 115 | __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); |
af9dafb1 LB |
116 | |
117 | /* | |
118 | * Enable timer 0. | |
119 | */ | |
c68ef2b5 | 120 | __raw_writel(0x03, mmp_timer_base + TMR_CER); |
49cbe786 EM |
121 | |
122 | local_irq_restore(flags); | |
af9dafb1 | 123 | |
49cbe786 EM |
124 | return 0; |
125 | } | |
126 | ||
127 | static void timer_set_mode(enum clock_event_mode mode, | |
128 | struct clock_event_device *dev) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | local_irq_save(flags); | |
133 | switch (mode) { | |
134 | case CLOCK_EVT_MODE_ONESHOT: | |
135 | case CLOCK_EVT_MODE_UNUSED: | |
136 | case CLOCK_EVT_MODE_SHUTDOWN: | |
137 | /* disable the matching interrupt */ | |
c68ef2b5 | 138 | __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); |
49cbe786 EM |
139 | break; |
140 | case CLOCK_EVT_MODE_RESUME: | |
141 | case CLOCK_EVT_MODE_PERIODIC: | |
142 | break; | |
143 | } | |
144 | local_irq_restore(flags); | |
145 | } | |
146 | ||
147 | static struct clock_event_device ckevt = { | |
148 | .name = "clockevent", | |
149 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
49cbe786 EM |
150 | .rating = 200, |
151 | .set_next_event = timer_set_next_event, | |
152 | .set_mode = timer_set_mode, | |
153 | }; | |
154 | ||
f5c81a32 | 155 | static cycle_t clksrc_read(struct clocksource *cs) |
49cbe786 EM |
156 | { |
157 | return timer_read(); | |
158 | } | |
159 | ||
160 | static struct clocksource cksrc = { | |
161 | .name = "clocksource", | |
49cbe786 EM |
162 | .rating = 200, |
163 | .read = clksrc_read, | |
164 | .mask = CLOCKSOURCE_MASK(32), | |
165 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
166 | }; | |
167 | ||
168 | static void __init timer_config(void) | |
169 | { | |
c68ef2b5 | 170 | uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); |
49cbe786 | 171 | |
c68ef2b5 | 172 | __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ |
49cbe786 | 173 | |
7ce5ae39 LB |
174 | ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : |
175 | (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); | |
c68ef2b5 | 176 | __raw_writel(ccr, mmp_timer_base + TMR_CCR); |
49cbe786 | 177 | |
af9dafb1 | 178 | /* set timer 0 to periodic mode, and timer 1 to free-running mode */ |
c68ef2b5 | 179 | __raw_writel(0x2, mmp_timer_base + TMR_CMR); |
49cbe786 | 180 | |
c68ef2b5 HZ |
181 | __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */ |
182 | __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */ | |
183 | __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); | |
49cbe786 | 184 | |
c68ef2b5 HZ |
185 | __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */ |
186 | __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */ | |
187 | __raw_writel(0x0, mmp_timer_base + TMR_IER(1)); | |
7ce5ae39 | 188 | |
af9dafb1 | 189 | /* enable timer 1 counter */ |
c68ef2b5 | 190 | __raw_writel(0x2, mmp_timer_base + TMR_CER); |
49cbe786 EM |
191 | } |
192 | ||
193 | static struct irqaction timer_irq = { | |
194 | .name = "timer", | |
9929eedc | 195 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
49cbe786 EM |
196 | .handler = timer_interrupt, |
197 | .dev_id = &ckevt, | |
198 | }; | |
199 | ||
200 | void __init timer_init(int irq) | |
201 | { | |
202 | timer_config(); | |
203 | ||
11d73c56 | 204 | sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ); |
49cbe786 | 205 | |
49cbe786 EM |
206 | ckevt.cpumask = cpumask_of(0); |
207 | ||
49cbe786 EM |
208 | setup_irq(irq, &timer_irq); |
209 | ||
ea158119 UKK |
210 | clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ); |
211 | clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ, | |
838a2ae8 | 212 | MIN_DELTA, MAX_DELTA); |
49cbe786 | 213 | } |
c68ef2b5 HZ |
214 | |
215 | #ifdef CONFIG_OF | |
216 | static struct of_device_id mmp_timer_dt_ids[] = { | |
217 | { .compatible = "mrvl,mmp-timer", }, | |
218 | {} | |
219 | }; | |
220 | ||
221 | void __init mmp_dt_init_timer(void) | |
222 | { | |
223 | struct device_node *np; | |
224 | int irq, ret; | |
225 | ||
226 | np = of_find_matching_node(NULL, mmp_timer_dt_ids); | |
227 | if (!np) { | |
228 | ret = -ENODEV; | |
229 | goto out; | |
230 | } | |
231 | ||
232 | irq = irq_of_parse_and_map(np, 0); | |
233 | if (!irq) { | |
234 | ret = -EINVAL; | |
235 | goto out; | |
236 | } | |
237 | mmp_timer_base = of_iomap(np, 0); | |
238 | if (!mmp_timer_base) { | |
239 | ret = -ENOMEM; | |
240 | goto out; | |
241 | } | |
242 | timer_init(irq); | |
243 | return; | |
244 | out: | |
245 | pr_err("Failed to get timer from device tree with error:%d\n", ret); | |
246 | } | |
247 | #endif |