Commit | Line | Data |
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49cbe786 EM |
1 | /* |
2 | * linux/arch/arm/mach-mmp/time.c | |
3 | * | |
4 | * Support for clocksource and clockevents | |
5 | * | |
6 | * Copyright (C) 2008 Marvell International Ltd. | |
7 | * All rights reserved. | |
8 | * | |
9 | * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> | |
10 | * 2008-10-08: Bin Yang <bin.yang@marvell.com> | |
11 | * | |
25985edc | 12 | * The timers module actually includes three timers, each timer with up to |
49cbe786 EM |
13 | * three match comparators. Timer #0 is used here in free-running mode as |
14 | * the clock source, and match comparator #1 used as clock event device. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/clockchips.h> | |
25 | ||
26 | #include <linux/io.h> | |
27 | #include <linux/irq.h> | |
c68ef2b5 HZ |
28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
38ff87f7 | 31 | #include <linux/sched_clock.h> |
2f7e8fae | 32 | #include <asm/mach/time.h> |
49cbe786 | 33 | |
b501fd7b AB |
34 | #include "addr-map.h" |
35 | #include "regs-timers.h" | |
36 | #include "regs-apbc.h" | |
37 | #include "irqs.h" | |
38 | #include "cputype.h" | |
49cbe786 EM |
39 | #include "clock.h" |
40 | ||
ea158119 UKK |
41 | #ifdef CONFIG_CPU_MMP2 |
42 | #define MMP_CLOCK_FREQ 6500000 | |
43 | #else | |
44 | #define MMP_CLOCK_FREQ 3250000 | |
45 | #endif | |
46 | ||
49cbe786 EM |
47 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE |
48 | ||
49 | #define MAX_DELTA (0xfffffffe) | |
50 | #define MIN_DELTA (16) | |
51 | ||
c68ef2b5 HZ |
52 | static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; |
53 | ||
49cbe786 EM |
54 | /* |
55 | * FIXME: the timer needs some delay to stablize the counter capture | |
56 | */ | |
57 | static inline uint32_t timer_read(void) | |
58 | { | |
59 | int delay = 100; | |
60 | ||
c68ef2b5 | 61 | __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); |
49cbe786 EM |
62 | |
63 | while (delay--) | |
64 | cpu_relax(); | |
65 | ||
c68ef2b5 | 66 | return __raw_readl(mmp_timer_base + TMR_CVWR(1)); |
49cbe786 EM |
67 | } |
68 | ||
e5c0228d | 69 | static u64 notrace mmp_read_sched_clock(void) |
49cbe786 | 70 | { |
2f0778af | 71 | return timer_read(); |
49cbe786 EM |
72 | } |
73 | ||
74 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | |
75 | { | |
76 | struct clock_event_device *c = dev_id; | |
77 | ||
af9dafb1 LB |
78 | /* |
79 | * Clear pending interrupt status. | |
80 | */ | |
c68ef2b5 | 81 | __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); |
af9dafb1 LB |
82 | |
83 | /* | |
84 | * Disable timer 0. | |
85 | */ | |
c68ef2b5 | 86 | __raw_writel(0x02, mmp_timer_base + TMR_CER); |
af9dafb1 | 87 | |
49cbe786 | 88 | c->event_handler(c); |
af9dafb1 | 89 | |
49cbe786 EM |
90 | return IRQ_HANDLED; |
91 | } | |
92 | ||
93 | static int timer_set_next_event(unsigned long delta, | |
94 | struct clock_event_device *dev) | |
95 | { | |
af9dafb1 | 96 | unsigned long flags; |
49cbe786 EM |
97 | |
98 | local_irq_save(flags); | |
99 | ||
af9dafb1 LB |
100 | /* |
101 | * Disable timer 0. | |
102 | */ | |
c68ef2b5 | 103 | __raw_writel(0x02, mmp_timer_base + TMR_CER); |
af9dafb1 LB |
104 | |
105 | /* | |
106 | * Clear and enable timer match 0 interrupt. | |
107 | */ | |
c68ef2b5 HZ |
108 | __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); |
109 | __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); | |
49cbe786 | 110 | |
af9dafb1 LB |
111 | /* |
112 | * Setup new clockevent timer value. | |
113 | */ | |
c68ef2b5 | 114 | __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); |
af9dafb1 LB |
115 | |
116 | /* | |
117 | * Enable timer 0. | |
118 | */ | |
c68ef2b5 | 119 | __raw_writel(0x03, mmp_timer_base + TMR_CER); |
49cbe786 EM |
120 | |
121 | local_irq_restore(flags); | |
af9dafb1 | 122 | |
49cbe786 EM |
123 | return 0; |
124 | } | |
125 | ||
a785fb39 | 126 | static int timer_set_shutdown(struct clock_event_device *evt) |
49cbe786 EM |
127 | { |
128 | unsigned long flags; | |
129 | ||
130 | local_irq_save(flags); | |
a785fb39 VK |
131 | /* disable the matching interrupt */ |
132 | __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); | |
49cbe786 | 133 | local_irq_restore(flags); |
a785fb39 VK |
134 | |
135 | return 0; | |
49cbe786 EM |
136 | } |
137 | ||
138 | static struct clock_event_device ckevt = { | |
a785fb39 VK |
139 | .name = "clockevent", |
140 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
141 | .rating = 200, | |
142 | .set_next_event = timer_set_next_event, | |
143 | .set_state_shutdown = timer_set_shutdown, | |
144 | .set_state_oneshot = timer_set_shutdown, | |
49cbe786 EM |
145 | }; |
146 | ||
f5c81a32 | 147 | static cycle_t clksrc_read(struct clocksource *cs) |
49cbe786 EM |
148 | { |
149 | return timer_read(); | |
150 | } | |
151 | ||
152 | static struct clocksource cksrc = { | |
153 | .name = "clocksource", | |
49cbe786 EM |
154 | .rating = 200, |
155 | .read = clksrc_read, | |
156 | .mask = CLOCKSOURCE_MASK(32), | |
157 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
158 | }; | |
159 | ||
160 | static void __init timer_config(void) | |
161 | { | |
c68ef2b5 | 162 | uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); |
49cbe786 | 163 | |
c68ef2b5 | 164 | __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ |
49cbe786 | 165 | |
7ce5ae39 LB |
166 | ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : |
167 | (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); | |
c68ef2b5 | 168 | __raw_writel(ccr, mmp_timer_base + TMR_CCR); |
49cbe786 | 169 | |
af9dafb1 | 170 | /* set timer 0 to periodic mode, and timer 1 to free-running mode */ |
c68ef2b5 | 171 | __raw_writel(0x2, mmp_timer_base + TMR_CMR); |
49cbe786 | 172 | |
c68ef2b5 HZ |
173 | __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */ |
174 | __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */ | |
175 | __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); | |
49cbe786 | 176 | |
c68ef2b5 HZ |
177 | __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */ |
178 | __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */ | |
179 | __raw_writel(0x0, mmp_timer_base + TMR_IER(1)); | |
7ce5ae39 | 180 | |
af9dafb1 | 181 | /* enable timer 1 counter */ |
c68ef2b5 | 182 | __raw_writel(0x2, mmp_timer_base + TMR_CER); |
49cbe786 EM |
183 | } |
184 | ||
185 | static struct irqaction timer_irq = { | |
186 | .name = "timer", | |
9929eedc | 187 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
49cbe786 EM |
188 | .handler = timer_interrupt, |
189 | .dev_id = &ckevt, | |
190 | }; | |
191 | ||
192 | void __init timer_init(int irq) | |
193 | { | |
194 | timer_config(); | |
195 | ||
11d73c56 | 196 | sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ); |
49cbe786 | 197 | |
49cbe786 EM |
198 | ckevt.cpumask = cpumask_of(0); |
199 | ||
49cbe786 EM |
200 | setup_irq(irq, &timer_irq); |
201 | ||
ea158119 UKK |
202 | clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ); |
203 | clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ, | |
838a2ae8 | 204 | MIN_DELTA, MAX_DELTA); |
49cbe786 | 205 | } |
c68ef2b5 HZ |
206 | |
207 | #ifdef CONFIG_OF | |
444d2d33 | 208 | static const struct of_device_id mmp_timer_dt_ids[] = { |
c68ef2b5 HZ |
209 | { .compatible = "mrvl,mmp-timer", }, |
210 | {} | |
211 | }; | |
212 | ||
213 | void __init mmp_dt_init_timer(void) | |
214 | { | |
215 | struct device_node *np; | |
216 | int irq, ret; | |
217 | ||
218 | np = of_find_matching_node(NULL, mmp_timer_dt_ids); | |
219 | if (!np) { | |
220 | ret = -ENODEV; | |
221 | goto out; | |
222 | } | |
223 | ||
224 | irq = irq_of_parse_and_map(np, 0); | |
225 | if (!irq) { | |
226 | ret = -EINVAL; | |
227 | goto out; | |
228 | } | |
229 | mmp_timer_base = of_iomap(np, 0); | |
230 | if (!mmp_timer_base) { | |
231 | ret = -ENOMEM; | |
232 | goto out; | |
233 | } | |
234 | timer_init(irq); | |
235 | return; | |
236 | out: | |
237 | pr_err("Failed to get timer from device tree with error:%d\n", ret); | |
238 | } | |
239 | #endif |