[deliverable/linux.git] / arch / arm / mach-msm / board-qsd8x50.c

/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 */
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/err.h>
#include <linux/clkdev.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/io.h>
#include <asm/setup.h>

#include <mach/irqs.h>
#include <mach/sirc.h>
#include <mach/vreg.h>
#include <mach/clk.h>
#include <linux/platform_data/mmc-msm_sdcc.h>

#include "devices.h"
#include "common.h"

static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;

/* Leave smc91x resources empty here, as we'll fill them in
 * at run-time: they vary from board to board, and the true
 * configuration won't be known until boot.
 */
static struct resource smc91x_resources[] = {
	[0] = {
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name           = "smc91x",
	.id             = 0,
	.num_resources  = ARRAY_SIZE(smc91x_resources),
	.resource       = smc91x_resources,
};

static int __init msm_init_smc91x(void)
{
	if (machine_is_qsd8x50_surf()) {
		smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
		smc91x_resources[0].end   = qsd8x50_surf_smc91x_base + 0xff;
		smc91x_resources[1].start =
			gpio_to_irq(qsd8x50_surf_smc91x_gpio);
		smc91x_resources[1].end   =
			gpio_to_irq(qsd8x50_surf_smc91x_gpio);
		platform_device_register(&smc91x_device);
	}

	return 0;
}
module_init(msm_init_smc91x);

static int hsusb_phy_init_seq[] = {
	0x08, 0x31,	/* Increase HS Driver Amplitude */
	0x20, 0x32,	/* Enable and set Pre-Emphasis Depth to 10% */
	-1
};

static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
{
	int ret;

	if (assert) {
		ret = clk_reset(link_clk, CLK_RESET_ASSERT);
		if (ret)
			pr_err("usb hs_clk assert failed\n");
	} else {
		ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
		if (ret)
			pr_err("usb hs_clk deassert failed\n");
	}
	return ret;
}

static int hsusb_phy_clk_reset(struct clk *phy_clk)
{
	int ret;

	ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
	if (ret) {
		pr_err("usb phy clk assert failed\n");
		return ret;
	}
	usleep_range(10000, 12000);
	ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
	if (ret)
		pr_err("usb phy clk deassert failed\n");
	return ret;
}

static struct msm_otg_platform_data msm_otg_pdata = {
	.phy_init_seq		= hsusb_phy_init_seq,
	.mode                   = USB_DR_MODE_PERIPHERAL,
	.otg_control		= OTG_PHY_CONTROL,
	.link_clk_reset		= hsusb_link_clk_reset,
	.phy_clk_reset		= hsusb_phy_clk_reset,
};

static struct platform_device *devices[] __initdata = {
	&msm_clock_8x50,
	&msm_device_gpio_8x50,
	&msm_device_uart3,
	&msm_device_smd,
	&msm_device_otg,
	&msm_device_hsusb,
	&msm_device_hsusb_host,
};

static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
	{51, "sdc1_dat_3"},
	{52, "sdc1_dat_2"},
	{53, "sdc1_dat_1"},
	{54, "sdc1_dat_0"},
	{55, "sdc1_cmd"},
	{56, "sdc1_clk"}
};

static struct vreg *vreg_mmc;
static unsigned long vreg_sts;

static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
{
	int rc = 0;
	struct platform_device *pdev;

	pdev = container_of(dv, struct platform_device, dev);

	if (vdd == 0) {
		if (!vreg_sts)
			return 0;

		clear_bit(pdev->id, &vreg_sts);

		if (!vreg_sts) {
			rc = vreg_disable(vreg_mmc);
			if (rc)
				pr_err("vreg_mmc disable failed for slot "
						"%d: %d\n", pdev->id, rc);
		}
		return 0;
	}

	if (!vreg_sts) {
		rc = vreg_set_level(vreg_mmc, 2900);
		if (rc)
			pr_err("vreg_mmc set level failed for slot %d: %d\n",
					pdev->id, rc);
		rc = vreg_enable(vreg_mmc);
		if (rc)
			pr_err("vreg_mmc enable failed for slot %d: %d\n",
					pdev->id, rc);
	}
	set_bit(pdev->id, &vreg_sts);
	return 0;
}

static struct msm_mmc_gpio_data sdc1_gpio = {
	.gpio = sdc1_gpio_cfg,
	.size = ARRAY_SIZE(sdc1_gpio_cfg),
};

static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
	.ocr_mask	= MMC_VDD_27_28 | MMC_VDD_28_29,
	.translate_vdd	= msm_sdcc_setup_power,
	.gpio_data = &sdc1_gpio,
};

static void __init qsd8x50_init_mmc(void)
{
	vreg_mmc = vreg_get(NULL, "gp5");

	if (IS_ERR(vreg_mmc)) {
		pr_err("vreg get for vreg_mmc failed (%ld)\n",
				PTR_ERR(vreg_mmc));
		return;
	}

	msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
}

static void __init qsd8x50_map_io(void)
{
	msm_map_qsd8x50_io();
}

static void __init qsd8x50_init_irq(void)
{
	msm_init_irq();
	msm_init_sirc();
}

static void __init qsd8x50_init(void)
{
	msm_device_otg.dev.platform_data = &msm_otg_pdata;
	msm_device_hsusb.dev.parent = &msm_device_otg.dev;
	msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
	platform_add_devices(devices, ARRAY_SIZE(devices));
	qsd8x50_init_mmc();
}

static void __init qsd8x50_init_late(void)
{
	smd_debugfs_init();
}

MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
	.atag_offset = 0x100,
	.map_io = qsd8x50_map_io,
	.init_irq = qsd8x50_init_irq,
	.init_machine = qsd8x50_init,
	.init_late = qsd8x50_init_late,
	.init_time	= qsd8x50_timer_init,
MACHINE_END

MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
	.atag_offset = 0x100,
	.map_io = qsd8x50_map_io,
	.init_irq = qsd8x50_init_irq,
	.init_machine = qsd8x50_init,
	.init_late = qsd8x50_init_late,
	.init_time	= qsd8x50_timer_init,
MACHINE_END
Commit	Line	Data
8b4d95fc	1	/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
a32d2feb DW	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	15	* 02110-1301, USA.
	16	*/
2f8163ba	17	#include <linux/gpio.h>
a32d2feb DW	18	#include <linux/kernel.h>
a32d2feb DW	19	#include <linux/irq.h>
a32d2feb	20	#include <linux/platform_device.h>
a32d2feb	21	#include <linux/delay.h>
7032d512	22	#include <linux/usb/msm_hsusb.h>
8b4d95fc	23	#include <linux/err.h>
bd32344a	24	#include <linux/clkdev.h>
a32d2feb DW	25
	26	#include <asm/mach-types.h>
	27	#include <asm/mach/arch.h>
	28	#include <asm/io.h>
	29	#include <asm/setup.h>
	30
d1c0d43d DW	31	#include <mach/irqs.h>
d1c0d43d DW	32	#include <mach/sirc.h>
8b4d95fc	33	#include <mach/vreg.h>
5146d771	34	#include <mach/clk.h>
1ef21f63	35	#include <linux/platform_data/mmc-msm_sdcc.h>
a32d2feb DW	36
a32d2feb DW	37	#include "devices.h"
4312a7ef	38	#include "common.h"
a32d2feb	39
bcad6dc3 AK	40	static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
bcad6dc3 AK	41	static const unsigned qsd8x50_surf_smc91x_gpio __initconst = 156;
5d73c53b GB	42
	43	/* Leave smc91x resources empty here, as we'll fill them in
	44	* at run-time: they vary from board to board, and the true
	45	* configuration won't be known until boot.
	46	*/
7c63dedc	47	static struct resource smc91x_resources[] = {
5d73c53b GB	48	[0] = {
	49	.flags = IORESOURCE_MEM,
	50	},
	51	[1] = {
	52	.flags = IORESOURCE_IRQ,
	53	},
	54	};
	55
7c63dedc	56	static struct platform_device smc91x_device = {
5d73c53b GB	57	.name = "smc91x",
	58	.id = 0,
	59	.num_resources = ARRAY_SIZE(smc91x_resources),
	60	.resource = smc91x_resources,
	61	};
	62
	63	static int __init msm_init_smc91x(void)
	64	{
	65	if (machine_is_qsd8x50_surf()) {
	66	smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
	67	smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
	68	smc91x_resources[1].start =
	69	gpio_to_irq(qsd8x50_surf_smc91x_gpio);
	70	smc91x_resources[1].end =
	71	gpio_to_irq(qsd8x50_surf_smc91x_gpio);
	72	platform_device_register(&smc91x_device);
	73	}
	74
	75	return 0;
	76	}
	77	module_init(msm_init_smc91x);
	78
7032d512 PK	79	static int hsusb_phy_init_seq[] = {
	80	0x08, 0x31, /* Increase HS Driver Amplitude */
	81	0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */
	82	-1
	83	};
	84
5146d771 II	85	static int hsusb_link_clk_reset(struct clk *link_clk, bool assert)
	86	{
	87	int ret;
	88
	89	if (assert) {
	90	ret = clk_reset(link_clk, CLK_RESET_ASSERT);
	91	if (ret)
	92	pr_err("usb hs_clk assert failed\n");
	93	} else {
	94	ret = clk_reset(link_clk, CLK_RESET_DEASSERT);
	95	if (ret)
	96	pr_err("usb hs_clk deassert failed\n");
	97	}
	98	return ret;
	99	}
	100
	101	static int hsusb_phy_clk_reset(struct clk *phy_clk)
	102	{
	103	int ret;
	104
	105	ret = clk_reset(phy_clk, CLK_RESET_ASSERT);
	106	if (ret) {
	107	pr_err("usb phy clk assert failed\n");
	108	return ret;
	109	}
	110	usleep_range(10000, 12000);
	111	ret = clk_reset(phy_clk, CLK_RESET_DEASSERT);
	112	if (ret)
	113	pr_err("usb phy clk deassert failed\n");
	114	return ret;
	115	}
	116
7032d512 PK	117	static struct msm_otg_platform_data msm_otg_pdata = {
7032d512 PK	118	.phy_init_seq = hsusb_phy_init_seq,
971232cf	119	.mode = USB_DR_MODE_PERIPHERAL,
7032d512	120	.otg_control = OTG_PHY_CONTROL,
5146d771 II	121	.link_clk_reset = hsusb_link_clk_reset,
5146d771 II	122	.phy_clk_reset = hsusb_phy_clk_reset,
7032d512 PK	123	};
7032d512 PK	124
a32d2feb	125	static struct platform_device *devices[] __initdata = {
421faca0	126	&msm_clock_8x50,
7bce696b	127	&msm_device_gpio_8x50,
d1c0d43d	128	&msm_device_uart3,
88b52277	129	&msm_device_smd,
7032d512 PK	130	&msm_device_otg,
	131	&msm_device_hsusb,
	132	&msm_device_hsusb_host,
a32d2feb DW	133	};
a32d2feb DW	134
8b4d95fc ST	135	static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
	136	{51, "sdc1_dat_3"},
	137	{52, "sdc1_dat_2"},
	138	{53, "sdc1_dat_1"},
	139	{54, "sdc1_dat_0"},
	140	{55, "sdc1_cmd"},
	141	{56, "sdc1_clk"}
	142	};
	143
	144	static struct vreg *vreg_mmc;
	145	static unsigned long vreg_sts;
	146
	147	static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
	148	{
	149	int rc = 0;
	150	struct platform_device *pdev;
	151
	152	pdev = container_of(dv, struct platform_device, dev);
	153
	154	if (vdd == 0) {
	155	if (!vreg_sts)
	156	return 0;
	157
	158	clear_bit(pdev->id, &vreg_sts);
	159
	160	if (!vreg_sts) {
	161	rc = vreg_disable(vreg_mmc);
	162	if (rc)
	163	pr_err("vreg_mmc disable failed for slot "
	164	"%d: %d\n", pdev->id, rc);
	165	}
	166	return 0;
	167	}
	168
	169	if (!vreg_sts) {
	170	rc = vreg_set_level(vreg_mmc, 2900);
	171	if (rc)
	172	pr_err("vreg_mmc set level failed for slot %d: %d\n",
	173	pdev->id, rc);
	174	rc = vreg_enable(vreg_mmc);
	175	if (rc)
	176	pr_err("vreg_mmc enable failed for slot %d: %d\n",
	177	pdev->id, rc);
	178	}
	179	set_bit(pdev->id, &vreg_sts);
	180	return 0;
	181	}
	182
	183	static struct msm_mmc_gpio_data sdc1_gpio = {
	184	.gpio = sdc1_gpio_cfg,
	185	.size = ARRAY_SIZE(sdc1_gpio_cfg),
	186	};
	187
	188	static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
	189	.ocr_mask = MMC_VDD_27_28 \| MMC_VDD_28_29,
	190	.translate_vdd = msm_sdcc_setup_power,
	191	.gpio_data = &sdc1_gpio,
	192	};
	193
	194	static void __init qsd8x50_init_mmc(void)
	195	{
62f0988e	196	vreg_mmc = vreg_get(NULL, "gp5");
8b4d95fc ST	197
	198	if (IS_ERR(vreg_mmc)) {
	199	pr_err("vreg get for vreg_mmc failed (%ld)\n",
	200	PTR_ERR(vreg_mmc));
	201	return;
	202	}
	203
	204	msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
	205	}
	206
d1c0d43d	207	static void __init qsd8x50_map_io(void)
a32d2feb	208	{
d1c0d43d	209	msm_map_qsd8x50_io();
a32d2feb DW	210	}
a32d2feb DW	211
d1c0d43d	212	static void __init qsd8x50_init_irq(void)
a32d2feb	213	{
d1c0d43d DW	214	msm_init_irq();
d1c0d43d DW	215	msm_init_sirc();
a32d2feb DW	216	}
	217
	218	static void __init qsd8x50_init(void)
	219	{
7032d512 PK	220	msm_device_otg.dev.platform_data = &msm_otg_pdata;
	221	msm_device_hsusb.dev.parent = &msm_device_otg.dev;
	222	msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
a32d2feb	223	platform_add_devices(devices, ARRAY_SIZE(devices));
8b4d95fc	224	qsd8x50_init_mmc();
a32d2feb DW	225	}
a32d2feb DW	226
c633c531 SG	227	static void __init qsd8x50_init_late(void)
	228	{
	229	smd_debugfs_init();
	230	}
	231
a32d2feb	232	MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
f631dd41	233	.atag_offset = 0x100,
a32d2feb DW	234	.map_io = qsd8x50_map_io,
	235	.init_irq = qsd8x50_init_irq,
	236	.init_machine = qsd8x50_init,
c633c531	237	.init_late = qsd8x50_init_late,
6bb27d73	238	.init_time = qsd8x50_timer_init,
a32d2feb DW	239	MACHINE_END
a32d2feb DW	240
d1c0d43d	241	MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
f631dd41	242	.atag_offset = 0x100,
a32d2feb DW	243	.map_io = qsd8x50_map_io,
	244	.init_irq = qsd8x50_init_irq,
	245	.init_machine = qsd8x50_init,
c633c531	246	.init_late = qsd8x50_init_late,
6bb27d73	247	.init_time = qsd8x50_timer_init,
a32d2feb	248	MACHINE_END