[deliverable/linux.git] / arch / arm / mach-msm / clock-7x30.h

/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H

enum {
	L_7X30_NONE_CLK = -1,
	L_7X30_ADM_CLK,
	L_7X30_I2C_CLK,
	L_7X30_I2C_2_CLK,
	L_7X30_QUP_I2C_CLK,
	L_7X30_UART1DM_CLK,
	L_7X30_UART1DM_P_CLK,
	L_7X30_UART2DM_CLK,
	L_7X30_UART2DM_P_CLK,
	L_7X30_EMDH_CLK,
	L_7X30_EMDH_P_CLK,
	L_7X30_PMDH_CLK,
	L_7X30_PMDH_P_CLK,
	L_7X30_GRP_2D_CLK,
	L_7X30_GRP_2D_P_CLK,
	L_7X30_GRP_3D_SRC_CLK,
	L_7X30_GRP_3D_CLK,
	L_7X30_GRP_3D_P_CLK,
	L_7X30_IMEM_CLK,
	L_7X30_SDC1_CLK,
	L_7X30_SDC1_P_CLK,
	L_7X30_SDC2_CLK,
	L_7X30_SDC2_P_CLK,
	L_7X30_SDC3_CLK,
	L_7X30_SDC3_P_CLK,
	L_7X30_SDC4_CLK,
	L_7X30_SDC4_P_CLK,
	L_7X30_MDP_CLK,
	L_7X30_MDP_P_CLK,
	L_7X30_MDP_LCDC_PCLK_CLK,
	L_7X30_MDP_LCDC_PAD_PCLK_CLK,
	L_7X30_MDP_VSYNC_CLK,
	L_7X30_MI2S_CODEC_RX_M_CLK,
	L_7X30_MI2S_CODEC_RX_S_CLK,
	L_7X30_MI2S_CODEC_TX_M_CLK,
	L_7X30_MI2S_CODEC_TX_S_CLK,
	L_7X30_MI2S_M_CLK,
	L_7X30_MI2S_S_CLK,
	L_7X30_LPA_CODEC_CLK,
	L_7X30_LPA_CORE_CLK,
	L_7X30_LPA_P_CLK,
	L_7X30_MIDI_CLK,
	L_7X30_MDC_CLK,
	L_7X30_ROTATOR_IMEM_CLK,
	L_7X30_ROTATOR_P_CLK,
	L_7X30_SDAC_M_CLK,
	L_7X30_SDAC_CLK,
	L_7X30_UART1_CLK,
	L_7X30_UART2_CLK,
	L_7X30_UART3_CLK,
	L_7X30_TV_CLK,
	L_7X30_TV_DAC_CLK,
	L_7X30_TV_ENC_CLK,
	L_7X30_HDMI_CLK,
	L_7X30_TSIF_REF_CLK,
	L_7X30_TSIF_P_CLK,
	L_7X30_USB_HS_SRC_CLK,
	L_7X30_USB_HS_CLK,
	L_7X30_USB_HS_CORE_CLK,
	L_7X30_USB_HS_P_CLK,
	L_7X30_USB_HS2_CLK,
	L_7X30_USB_HS2_CORE_CLK,
	L_7X30_USB_HS2_P_CLK,
	L_7X30_USB_HS3_CLK,
	L_7X30_USB_HS3_CORE_CLK,
	L_7X30_USB_HS3_P_CLK,
	L_7X30_VFE_CLK,
	L_7X30_VFE_P_CLK,
	L_7X30_VFE_MDC_CLK,
	L_7X30_VFE_CAMIF_CLK,
	L_7X30_CAMIF_PAD_P_CLK,
	L_7X30_CAM_M_CLK,
	L_7X30_JPEG_CLK,
	L_7X30_JPEG_P_CLK,
	L_7X30_VPE_CLK,
	L_7X30_MFC_CLK,
	L_7X30_MFC_DIV2_CLK,
	L_7X30_MFC_P_CLK,
	L_7X30_SPI_CLK,
	L_7X30_SPI_P_CLK,
	L_7X30_CSI0_CLK,
	L_7X30_CSI0_VFE_CLK,
	L_7X30_CSI0_P_CLK,
	L_7X30_CSI1_CLK,
	L_7X30_CSI1_VFE_CLK,
	L_7X30_CSI1_P_CLK,
	L_7X30_GLBL_ROOT_CLK,

	L_7X30_AXI_LI_VG_CLK,
	L_7X30_AXI_LI_GRP_CLK,
	L_7X30_AXI_LI_JPEG_CLK,
	L_7X30_AXI_GRP_2D_CLK,
	L_7X30_AXI_MFC_CLK,
	L_7X30_AXI_VPE_CLK,
	L_7X30_AXI_LI_VFE_CLK,
	L_7X30_AXI_LI_APPS_CLK,
	L_7X30_AXI_MDP_CLK,
	L_7X30_AXI_IMEM_CLK,
	L_7X30_AXI_LI_ADSP_A_CLK,
	L_7X30_AXI_ROTATOR_CLK,

	L_7X30_NR_CLKS
};

struct clk_ops;
extern struct clk_ops clk_ops_7x30;

struct clk_ops *clk_7x30_is_local(uint32_t id);
int clk_7x30_init(void);

void pll_enable(uint32_t pll);
void pll_disable(uint32_t pll);

extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);

#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) {	\
	.con_id = clk_name, \
	.dev_id = clk_dev, \
	.clk = &(struct clk){ \
		.id = L_7X30_##clk_id, \
		.remote_id = P_##clk_id, \
		.flags = clk_flags, \
		.dbg_name = #clk_id, \
	}, \
	}

#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) {	\
	.con_id = clk_name, \
	.dev_id = clk_dev, \
	.clk = &(struct clk){ \
		.id = L_7X30_##l_id, \
		.remote_id = P_##r_id, \
		.flags = clk_flags, \
		.dbg_name = #l_id, \
		.ops = &clk_ops_pcom, \
	}, \
	}

#endif
Commit	Line	Data
37a298fb GB	1	/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
37a298fb GB	2	*
3162aa2f DB	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
37a298fb	6	*
3162aa2f DB	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
37a298fb GB	11	*/
	12
	13	#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
	14	#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
	15
	16	enum {
	17	L_7X30_NONE_CLK = -1,
	18	L_7X30_ADM_CLK,
	19	L_7X30_I2C_CLK,
	20	L_7X30_I2C_2_CLK,
	21	L_7X30_QUP_I2C_CLK,
	22	L_7X30_UART1DM_CLK,
	23	L_7X30_UART1DM_P_CLK,
	24	L_7X30_UART2DM_CLK,
	25	L_7X30_UART2DM_P_CLK,
	26	L_7X30_EMDH_CLK,
	27	L_7X30_EMDH_P_CLK,
	28	L_7X30_PMDH_CLK,
	29	L_7X30_PMDH_P_CLK,
	30	L_7X30_GRP_2D_CLK,
	31	L_7X30_GRP_2D_P_CLK,
	32	L_7X30_GRP_3D_SRC_CLK,
	33	L_7X30_GRP_3D_CLK,
	34	L_7X30_GRP_3D_P_CLK,
	35	L_7X30_IMEM_CLK,
	36	L_7X30_SDC1_CLK,
	37	L_7X30_SDC1_P_CLK,
	38	L_7X30_SDC2_CLK,
	39	L_7X30_SDC2_P_CLK,
	40	L_7X30_SDC3_CLK,
	41	L_7X30_SDC3_P_CLK,
	42	L_7X30_SDC4_CLK,
	43	L_7X30_SDC4_P_CLK,
	44	L_7X30_MDP_CLK,
	45	L_7X30_MDP_P_CLK,
	46	L_7X30_MDP_LCDC_PCLK_CLK,
	47	L_7X30_MDP_LCDC_PAD_PCLK_CLK,
	48	L_7X30_MDP_VSYNC_CLK,
	49	L_7X30_MI2S_CODEC_RX_M_CLK,
	50	L_7X30_MI2S_CODEC_RX_S_CLK,
	51	L_7X30_MI2S_CODEC_TX_M_CLK,
	52	L_7X30_MI2S_CODEC_TX_S_CLK,
	53	L_7X30_MI2S_M_CLK,
	54	L_7X30_MI2S_S_CLK,
	55	L_7X30_LPA_CODEC_CLK,
	56	L_7X30_LPA_CORE_CLK,
	57	L_7X30_LPA_P_CLK,
	58	L_7X30_MIDI_CLK,
	59	L_7X30_MDC_CLK,
	60	L_7X30_ROTATOR_IMEM_CLK,
	61	L_7X30_ROTATOR_P_CLK,
	62	L_7X30_SDAC_M_CLK,
	63	L_7X30_SDAC_CLK,
	64	L_7X30_UART1_CLK,
	65	L_7X30_UART2_CLK,
	66	L_7X30_UART3_CLK,
	67	L_7X30_TV_CLK,
	68	L_7X30_TV_DAC_CLK,
	69	L_7X30_TV_ENC_CLK,
	70	L_7X30_HDMI_CLK,
	71	L_7X30_TSIF_REF_CLK,
	72	L_7X30_TSIF_P_CLK,
	73	L_7X30_USB_HS_SRC_CLK,
	74	L_7X30_USB_HS_CLK,
75	L_7X30_USB_HS_CORE_CLK,
76	L_7X30_USB_HS_P_CLK,
77	L_7X30_USB_HS2_CLK,
78	L_7X30_USB_HS2_CORE_CLK,
79	L_7X30_USB_HS2_P_CLK,
80	L_7X30_USB_HS3_CLK,
81	L_7X30_USB_HS3_CORE_CLK,
82	L_7X30_USB_HS3_P_CLK,
83	L_7X30_VFE_CLK,
84	L_7X30_VFE_P_CLK,
85	L_7X30_VFE_MDC_CLK,
86	L_7X30_VFE_CAMIF_CLK,
87	L_7X30_CAMIF_PAD_P_CLK,
88	L_7X30_CAM_M_CLK,
89	L_7X30_JPEG_CLK,
90	L_7X30_JPEG_P_CLK,
91	L_7X30_VPE_CLK,
92	L_7X30_MFC_CLK,
93	L_7X30_MFC_DIV2_CLK,
94	L_7X30_MFC_P_CLK,
95	L_7X30_SPI_CLK,
96	L_7X30_SPI_P_CLK,
97	L_7X30_CSI0_CLK,
98	L_7X30_CSI0_VFE_CLK,
99	L_7X30_CSI0_P_CLK,
100	L_7X30_CSI1_CLK,
101	L_7X30_CSI1_VFE_CLK,
102	L_7X30_CSI1_P_CLK,
103	L_7X30_GLBL_ROOT_CLK,
104
105	L_7X30_AXI_LI_VG_CLK,
106	L_7X30_AXI_LI_GRP_CLK,
107	L_7X30_AXI_LI_JPEG_CLK,
108	L_7X30_AXI_GRP_2D_CLK,
109	L_7X30_AXI_MFC_CLK,
110	L_7X30_AXI_VPE_CLK,
111	L_7X30_AXI_LI_VFE_CLK,
112	L_7X30_AXI_LI_APPS_CLK,
113	L_7X30_AXI_MDP_CLK,
114	L_7X30_AXI_IMEM_CLK,
115	L_7X30_AXI_LI_ADSP_A_CLK,
116	L_7X30_AXI_ROTATOR_CLK,
117
118	L_7X30_NR_CLKS
119	};
120
121	struct clk_ops;
122	extern struct clk_ops clk_ops_7x30;
123
124	struct clk_ops *clk_7x30_is_local(uint32_t id);
125	int clk_7x30_init(void);
126
127	void pll_enable(uint32_t pll);
128	void pll_disable(uint32_t pll);
129
130	extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
131
132	#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \
bd32344a SB	133	.con_id = clk_name, \
	134	.dev_id = clk_dev, \
	135	.clk = &(struct clk){ \
	136	.id = L_7X30_##clk_id, \
	137	.remote_id = P_##clk_id, \
	138	.flags = clk_flags, \
	139	.dbg_name = #clk_id, \
	140	}, \
37a298fb GB	141	}
	142
	143	#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \
bd32344a SB	144	.con_id = clk_name, \
	145	.dev_id = clk_dev, \
	146	.clk = &(struct clk){ \
	147	.id = L_7X30_##l_id, \
	148	.remote_id = P_##r_id, \
	149	.flags = clk_flags, \
	150	.dbg_name = #l_id, \
	151	.ops = &clk_ops_pcom, \
	152	}, \
37a298fb GB	153	}
	154
	155	#endif