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62a6cc57 DW |
1 | /* |
2 | * Copyright (C) 2008 Google, Inc. | |
d41cb8c9 | 3 | * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
62a6cc57 DW |
4 | * |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/platform_device.h> | |
bd32344a | 18 | #include <linux/clkdev.h> |
62a6cc57 | 19 | #include <linux/dma-mapping.h> |
bd32344a | 20 | |
62a6cc57 DW |
21 | #include <mach/irqs.h> |
22 | #include <mach/msm_iomap.h> | |
23 | #include <mach/dma.h> | |
24 | #include <mach/board.h> | |
25 | ||
26 | #include "devices.h" | |
27 | ||
28 | #include <asm/mach/flash.h> | |
29 | ||
1ef21f63 | 30 | #include <linux/platform_data/mmc-msm_sdcc.h> |
421faca0 | 31 | #include "clock.h" |
ce1c80fb | 32 | #include "clock-pcom.h" |
62a6cc57 | 33 | |
7bce696b SB |
34 | static struct resource msm_gpio_resources[] = { |
35 | { | |
36 | .start = 64 + 165 + 9, | |
37 | .end = 64 + 165 + 9, | |
38 | .flags = IORESOURCE_IRQ, | |
39 | }, | |
40 | { | |
41 | .start = 64 + 165 + 10, | |
42 | .end = 64 + 165 + 10, | |
43 | .flags = IORESOURCE_IRQ, | |
44 | }, | |
45 | { | |
46 | .start = 0xa9000800, | |
47 | .end = 0xa9000800 + SZ_4K - 1, | |
48 | .flags = IORESOURCE_MEM, | |
49 | .name = "gpio1" | |
50 | }, | |
51 | { | |
52 | .start = 0xa9100C00, | |
53 | .end = 0xa9100C00 + SZ_4K - 1, | |
54 | .flags = IORESOURCE_MEM, | |
55 | .name = "gpio2" | |
56 | }, | |
57 | }; | |
58 | ||
59 | struct platform_device msm_device_gpio_8x50 = { | |
60 | .name = "gpio-msm-8x50", | |
61 | .num_resources = ARRAY_SIZE(msm_gpio_resources), | |
62 | .resource = msm_gpio_resources, | |
63 | }; | |
64 | ||
62a6cc57 DW |
65 | static struct resource resources_uart3[] = { |
66 | { | |
67 | .start = INT_UART3, | |
68 | .end = INT_UART3, | |
69 | .flags = IORESOURCE_IRQ, | |
70 | }, | |
71 | { | |
72 | .start = MSM_UART3_PHYS, | |
73 | .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, | |
74 | .flags = IORESOURCE_MEM, | |
d41cb8c9 | 75 | .name = "uart_resource" |
62a6cc57 DW |
76 | }, |
77 | }; | |
78 | ||
79 | struct platform_device msm_device_uart3 = { | |
80 | .name = "msm_serial", | |
81 | .id = 2, | |
82 | .num_resources = ARRAY_SIZE(resources_uart3), | |
83 | .resource = resources_uart3, | |
84 | }; | |
85 | ||
88b52277 NV |
86 | struct platform_device msm_device_smd = { |
87 | .name = "msm_smd", | |
88 | .id = -1, | |
89 | }; | |
90 | ||
7032d512 PK |
91 | static struct resource resources_otg[] = { |
92 | { | |
93 | .start = MSM_HSUSB_PHYS, | |
94 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | |
95 | .flags = IORESOURCE_MEM, | |
96 | }, | |
97 | { | |
98 | .start = INT_USB_HS, | |
99 | .end = INT_USB_HS, | |
100 | .flags = IORESOURCE_IRQ, | |
101 | }, | |
102 | }; | |
103 | ||
104 | struct platform_device msm_device_otg = { | |
105 | .name = "msm_otg", | |
106 | .id = -1, | |
107 | .num_resources = ARRAY_SIZE(resources_otg), | |
108 | .resource = resources_otg, | |
109 | .dev = { | |
110 | .coherent_dma_mask = 0xffffffff, | |
111 | }, | |
112 | }; | |
113 | ||
114 | static struct resource resources_hsusb[] = { | |
115 | { | |
116 | .start = MSM_HSUSB_PHYS, | |
117 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | |
118 | .flags = IORESOURCE_MEM, | |
119 | }, | |
120 | { | |
121 | .start = INT_USB_HS, | |
122 | .end = INT_USB_HS, | |
123 | .flags = IORESOURCE_IRQ, | |
124 | }, | |
125 | }; | |
126 | ||
127 | struct platform_device msm_device_hsusb = { | |
128 | .name = "msm_hsusb", | |
129 | .id = -1, | |
130 | .num_resources = ARRAY_SIZE(resources_hsusb), | |
131 | .resource = resources_hsusb, | |
132 | .dev = { | |
133 | .coherent_dma_mask = 0xffffffff, | |
134 | }, | |
135 | }; | |
136 | ||
137 | static u64 dma_mask = 0xffffffffULL; | |
138 | static struct resource resources_hsusb_host[] = { | |
139 | { | |
140 | .start = MSM_HSUSB_PHYS, | |
141 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | |
142 | .flags = IORESOURCE_MEM, | |
143 | }, | |
144 | { | |
145 | .start = INT_USB_HS, | |
146 | .end = INT_USB_HS, | |
147 | .flags = IORESOURCE_IRQ, | |
148 | }, | |
149 | }; | |
150 | ||
151 | struct platform_device msm_device_hsusb_host = { | |
152 | .name = "msm_hsusb_host", | |
153 | .id = -1, | |
154 | .num_resources = ARRAY_SIZE(resources_hsusb_host), | |
155 | .resource = resources_hsusb_host, | |
156 | .dev = { | |
157 | .dma_mask = &dma_mask, | |
158 | .coherent_dma_mask = 0xffffffffULL, | |
159 | }, | |
160 | }; | |
161 | ||
8b4d95fc ST |
162 | static struct resource resources_sdc1[] = { |
163 | { | |
164 | .start = MSM_SDC1_PHYS, | |
165 | .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1, | |
166 | .flags = IORESOURCE_MEM, | |
167 | }, | |
168 | { | |
169 | .start = INT_SDC1_0, | |
170 | .end = INT_SDC1_0, | |
171 | .flags = IORESOURCE_IRQ, | |
172 | .name = "cmd_irq", | |
173 | }, | |
8b4d95fc ST |
174 | { |
175 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
176 | .name = "status_irq" | |
177 | }, | |
178 | { | |
179 | .start = 8, | |
180 | .end = 8, | |
181 | .flags = IORESOURCE_DMA, | |
182 | }, | |
183 | }; | |
184 | ||
185 | static struct resource resources_sdc2[] = { | |
186 | { | |
187 | .start = MSM_SDC2_PHYS, | |
188 | .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1, | |
189 | .flags = IORESOURCE_MEM, | |
190 | }, | |
191 | { | |
192 | .start = INT_SDC2_0, | |
193 | .end = INT_SDC2_0, | |
194 | .flags = IORESOURCE_IRQ, | |
195 | .name = "cmd_irq", | |
8b4d95fc ST |
196 | }, |
197 | { | |
198 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
199 | .name = "status_irq" | |
200 | }, | |
201 | { | |
202 | .start = 8, | |
203 | .end = 8, | |
204 | .flags = IORESOURCE_DMA, | |
205 | }, | |
206 | }; | |
207 | ||
208 | static struct resource resources_sdc3[] = { | |
209 | { | |
210 | .start = MSM_SDC3_PHYS, | |
211 | .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1, | |
212 | .flags = IORESOURCE_MEM, | |
213 | }, | |
214 | { | |
215 | .start = INT_SDC3_0, | |
216 | .end = INT_SDC3_0, | |
217 | .flags = IORESOURCE_IRQ, | |
218 | .name = "cmd_irq", | |
8b4d95fc ST |
219 | }, |
220 | { | |
221 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
222 | .name = "status_irq" | |
223 | }, | |
224 | { | |
225 | .start = 8, | |
226 | .end = 8, | |
227 | .flags = IORESOURCE_DMA, | |
228 | }, | |
229 | }; | |
230 | ||
231 | static struct resource resources_sdc4[] = { | |
232 | { | |
233 | .start = MSM_SDC4_PHYS, | |
234 | .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1, | |
235 | .flags = IORESOURCE_MEM, | |
236 | }, | |
237 | { | |
238 | .start = INT_SDC4_0, | |
239 | .end = INT_SDC4_0, | |
240 | .flags = IORESOURCE_IRQ, | |
241 | .name = "cmd_irq", | |
8b4d95fc ST |
242 | }, |
243 | { | |
244 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
245 | .name = "status_irq" | |
246 | }, | |
247 | { | |
248 | .start = 8, | |
249 | .end = 8, | |
250 | .flags = IORESOURCE_DMA, | |
251 | }, | |
252 | }; | |
253 | ||
254 | struct platform_device msm_device_sdc1 = { | |
255 | .name = "msm_sdcc", | |
256 | .id = 1, | |
257 | .num_resources = ARRAY_SIZE(resources_sdc1), | |
258 | .resource = resources_sdc1, | |
259 | .dev = { | |
260 | .coherent_dma_mask = 0xffffffff, | |
261 | }, | |
262 | }; | |
263 | ||
264 | struct platform_device msm_device_sdc2 = { | |
265 | .name = "msm_sdcc", | |
266 | .id = 2, | |
267 | .num_resources = ARRAY_SIZE(resources_sdc2), | |
268 | .resource = resources_sdc2, | |
269 | .dev = { | |
270 | .coherent_dma_mask = 0xffffffff, | |
271 | }, | |
272 | }; | |
273 | ||
274 | struct platform_device msm_device_sdc3 = { | |
275 | .name = "msm_sdcc", | |
276 | .id = 3, | |
277 | .num_resources = ARRAY_SIZE(resources_sdc3), | |
278 | .resource = resources_sdc3, | |
279 | .dev = { | |
280 | .coherent_dma_mask = 0xffffffff, | |
281 | }, | |
282 | }; | |
283 | ||
284 | struct platform_device msm_device_sdc4 = { | |
285 | .name = "msm_sdcc", | |
286 | .id = 4, | |
287 | .num_resources = ARRAY_SIZE(resources_sdc4), | |
288 | .resource = resources_sdc4, | |
289 | .dev = { | |
290 | .coherent_dma_mask = 0xffffffff, | |
291 | }, | |
292 | }; | |
293 | ||
294 | static struct platform_device *msm_sdcc_devices[] __initdata = { | |
295 | &msm_device_sdc1, | |
296 | &msm_device_sdc2, | |
297 | &msm_device_sdc3, | |
298 | &msm_device_sdc4, | |
299 | }; | |
300 | ||
301 | int __init msm_add_sdcc(unsigned int controller, | |
302 | struct msm_mmc_platform_data *plat, | |
303 | unsigned int stat_irq, unsigned long stat_irq_flags) | |
304 | { | |
305 | struct platform_device *pdev; | |
306 | struct resource *res; | |
307 | ||
308 | if (controller < 1 || controller > 4) | |
309 | return -EINVAL; | |
310 | ||
311 | pdev = msm_sdcc_devices[controller-1]; | |
312 | pdev->dev.platform_data = plat; | |
313 | ||
314 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); | |
315 | if (!res) | |
316 | return -EINVAL; | |
317 | else if (stat_irq) { | |
318 | res->start = res->end = stat_irq; | |
319 | res->flags &= ~IORESOURCE_DISABLED; | |
320 | res->flags |= stat_irq_flags; | |
321 | } | |
322 | ||
323 | return platform_device_register(pdev); | |
324 | } | |
325 | ||
8cc7f533 | 326 | static struct clk_pcom_desc msm_clocks_8x50[] = { |
62a6cc57 | 327 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
f689ac98 | 328 | CLK_PCOM("ce_clk", CE_CLK, NULL, 0), |
62a6cc57 DW |
329 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), |
330 | CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), | |
331 | CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), | |
332 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX), | |
333 | CLK_PCOM("gp_clk", GP_CLK, NULL, 0), | |
334 | CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0), | |
f689ac98 | 335 | CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0), |
62a6cc57 DW |
336 | CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), |
337 | CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), | |
338 | CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), | |
339 | CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0), | |
340 | CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), | |
341 | CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), | |
342 | CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0), | |
343 | CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0), | |
344 | CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0), | |
345 | CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), | |
346 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), | |
347 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), | |
bd32344a SB |
348 | CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), |
349 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), | |
350 | CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), | |
351 | CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), | |
352 | CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), | |
353 | CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), | |
354 | CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), | |
355 | CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), | |
62a6cc57 DW |
356 | CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), |
357 | CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), | |
358 | CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), | |
359 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), | |
360 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), | |
f689ac98 SB |
361 | CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF), |
362 | CLK_PCOM("uart_clk", UART2_CLK, NULL, 0), | |
bd32344a | 363 | CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), |
f689ac98 SB |
364 | CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF), |
365 | CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0), | |
62a6cc57 DW |
366 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), |
367 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), | |
368 | CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), | |
369 | CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN), | |
370 | CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), | |
371 | CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), | |
372 | CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF), | |
373 | CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF), | |
374 | CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF), | |
375 | CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF), | |
376 | CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF), | |
377 | CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), | |
378 | }; | |
379 | ||
421faca0 SB |
380 | static struct pcom_clk_pdata msm_clock_8x50_pdata = { |
381 | .lookup = msm_clocks_8x50, | |
382 | .num_lookups = ARRAY_SIZE(msm_clocks_8x50), | |
383 | }; | |
62a6cc57 | 384 | |
421faca0 SB |
385 | struct platform_device msm_clock_8x50 = { |
386 | .name = "msm-clock-pcom", | |
387 | .dev.platform_data = &msm_clock_8x50_pdata, | |
388 | }; |