Commit | Line | Data |
---|---|---|
184d252a DW |
1 | /* |
2 | * Copyright (C) 2007 Google, Inc. | |
8c27e6f3 | 3 | * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved. |
184d252a DW |
4 | * Author: Brian Swetland <swetland@google.com> |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * | |
16 | * The MSM peripherals are spread all over across 768MB of physical | |
17 | * space, which makes just having a simple IO_ADDRESS macro to slide | |
18 | * them into the right virtual location rough. Instead, we will | |
19 | * provide a master phys->virt mapping for peripherals here. | |
20 | * | |
21 | */ | |
22 | ||
23 | #ifndef __ASM_ARCH_MSM_IOMAP_7X30_H | |
24 | #define __ASM_ARCH_MSM_IOMAP_7X30_H | |
25 | ||
26 | /* Physical base address and size of peripherals. | |
27 | * Ordered by the virtual base addresses they will be mapped at. | |
28 | * | |
29 | * MSM_VIC_BASE must be an value that can be loaded via a "mov" | |
30 | * instruction, otherwise entry-macro.S will not compile. | |
31 | * | |
32 | * If you add or remove entries here, you'll want to edit the | |
33 | * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your | |
34 | * changes. | |
35 | * | |
36 | */ | |
37 | ||
38 | #define MSM_VIC_BASE IOMEM(0xE0000000) | |
39 | #define MSM_VIC_PHYS 0xC0080000 | |
40 | #define MSM_VIC_SIZE SZ_4K | |
41 | ||
8c27e6f3 DB |
42 | #define MSM7X30_CSR_PHYS 0xC0100000 |
43 | #define MSM7X30_CSR_SIZE SZ_4K | |
184d252a DW |
44 | |
45 | #define MSM_DMOV_BASE IOMEM(0xE0002000) | |
46 | #define MSM_DMOV_PHYS 0xAC400000 | |
47 | #define MSM_DMOV_SIZE SZ_4K | |
48 | ||
03db0729 DB |
49 | #define MSM7X30_GPIO1_PHYS 0xAC001000 |
50 | #define MSM7X30_GPIO1_SIZE SZ_4K | |
184d252a | 51 | |
03db0729 DB |
52 | #define MSM7X30_GPIO2_PHYS 0xAC101000 |
53 | #define MSM7X30_GPIO2_SIZE SZ_4K | |
184d252a DW |
54 | |
55 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) | |
56 | #define MSM_CLK_CTL_PHYS 0xAB800000 | |
57 | #define MSM_CLK_CTL_SIZE SZ_4K | |
58 | ||
59 | #define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000) | |
60 | #define MSM_CLK_CTL_SH2_PHYS 0xABA01000 | |
61 | #define MSM_CLK_CTL_SH2_SIZE SZ_4K | |
62 | ||
63 | #define MSM_ACC_BASE IOMEM(0xE0007000) | |
64 | #define MSM_ACC_PHYS 0xC0101000 | |
65 | #define MSM_ACC_SIZE SZ_4K | |
66 | ||
67 | #define MSM_SAW_BASE IOMEM(0xE0008000) | |
68 | #define MSM_SAW_PHYS 0xC0102000 | |
69 | #define MSM_SAW_SIZE SZ_4K | |
70 | ||
71 | #define MSM_GCC_BASE IOMEM(0xE0009000) | |
72 | #define MSM_GCC_PHYS 0xC0182000 | |
73 | #define MSM_GCC_SIZE SZ_4K | |
74 | ||
75 | #define MSM_TCSR_BASE IOMEM(0xE000A000) | |
76 | #define MSM_TCSR_PHYS 0xAB600000 | |
77 | #define MSM_TCSR_SIZE SZ_4K | |
78 | ||
79 | #define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) | |
80 | #define MSM_SHARED_RAM_PHYS 0x00100000 | |
81 | #define MSM_SHARED_RAM_SIZE SZ_1M | |
82 | ||
83 | #define MSM_UART1_PHYS 0xACA00000 | |
84 | #define MSM_UART1_SIZE SZ_4K | |
85 | ||
86 | #define MSM_UART2_PHYS 0xACB00000 | |
87 | #define MSM_UART2_SIZE SZ_4K | |
88 | ||
89 | #define MSM_UART3_PHYS 0xACC00000 | |
90 | #define MSM_UART3_SIZE SZ_4K | |
91 | ||
184d252a DW |
92 | #define MSM_MDC_BASE IOMEM(0xE0200000) |
93 | #define MSM_MDC_PHYS 0xAA500000 | |
94 | #define MSM_MDC_SIZE SZ_1M | |
95 | ||
96 | #define MSM_AD5_BASE IOMEM(0xE0300000) | |
97 | #define MSM_AD5_PHYS 0xA7000000 | |
98 | #define MSM_AD5_SIZE (SZ_1M*13) | |
99 | ||
5155e2c7 PK |
100 | #define MSM_HSUSB_PHYS 0xA3600000 |
101 | #define MSM_HSUSB_SIZE SZ_1K | |
102 | ||
184d252a | 103 | #endif |