Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
[deliverable/linux.git] / arch / arm / mach-msm / io.c
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3042102a
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1/* arch/arm/mach-msm/io.c
2 *
cf62ffae 3 * MSM7K, QSD io support
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4 *
5 * Copyright (C) 2007 Google, Inc.
8c27e6f3 6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
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7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
dc28094b 23#include <linux/export.h>
3042102a 24
a09e64fb 25#include <mach/hardware.h>
3042102a 26#include <asm/page.h>
a09e64fb 27#include <mach/msm_iomap.h>
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28#include <asm/mach/map.h>
29
a09e64fb 30#include <mach/board.h>
3042102a 31
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32#include "common.h"
33
90eb385f 34#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
bcc0f6af 35 .virtual = (unsigned long) MSM_##name##_BASE, \
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36 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
37 .length = chip##_##name##_SIZE, \
90eb385f 38 .type = mem_type, \
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39 }
40
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41#define MSM_DEVICE_TYPE(name, mem_type) \
42 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
43#define MSM_CHIP_DEVICE(name, chip) \
44 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
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45#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
46
e63770ac 47#if defined(CONFIG_ARCH_MSM7X00A)
3042102a 48static struct map_desc msm_io_desc[] __initdata = {
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49 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
50 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
51 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
52 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
53 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
54 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
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55#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
56 defined(CONFIG_DEBUG_MSM_UART3)
90eb385f 57 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
6339f669 58#endif
3042102a 59 {
bcc0f6af 60 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
cf62ffae 61 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
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62 .length = MSM_SHARED_RAM_SIZE,
63 .type = MT_DEVICE,
64 },
65};
66
67void __init msm_map_common_io(void)
68{
69 /* Make sure the peripheral register window is closed, since
70 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
71 * pages are peripheral interface or not.
72 */
73 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
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74 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
75}
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76#endif
77
78#ifdef CONFIG_ARCH_QSD8X50
79static struct map_desc qsd8x50_io_desc[] __initdata = {
80 MSM_DEVICE(VIC),
8c27e6f3 81 MSM_CHIP_DEVICE(CSR, QSD8X50),
cf62ffae 82 MSM_DEVICE(DMOV),
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83 MSM_CHIP_DEVICE(GPIO1, QSD8X50),
84 MSM_CHIP_DEVICE(GPIO2, QSD8X50),
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85 MSM_DEVICE(CLK_CTL),
86 MSM_DEVICE(SIRC),
87 MSM_DEVICE(SCPLL),
88 MSM_DEVICE(AD5),
89 MSM_DEVICE(MDC),
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90#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
91 defined(CONFIG_DEBUG_MSM_UART3)
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92 MSM_DEVICE(DEBUG_UART),
93#endif
94 {
95 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
96 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
97 .length = MSM_SHARED_RAM_SIZE,
98 .type = MT_DEVICE,
99 },
100};
101
102void __init msm_map_qsd8x50_io(void)
103{
104 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
105}
106#endif /* CONFIG_ARCH_QSD8X50 */
3042102a 107
6cf6dfef
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108#ifdef CONFIG_ARCH_MSM8X60
109static struct map_desc msm8x60_io_desc[] __initdata = {
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110 MSM_CHIP_DEVICE(TMR, MSM8X60),
111 MSM_CHIP_DEVICE(TMR0, MSM8X60),
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112#ifdef CONFIG_DEBUG_MSM8660_UART
113 MSM_DEVICE(DEBUG_UART),
114#endif
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115};
116
117void __init msm_map_msm8x60_io(void)
118{
119 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
120}
121#endif /* CONFIG_ARCH_MSM8X60 */
122
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123#ifdef CONFIG_ARCH_MSM8960
124static struct map_desc msm8960_io_desc[] __initdata = {
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125 MSM_CHIP_DEVICE(TMR, MSM8960),
126 MSM_CHIP_DEVICE(TMR0, MSM8960),
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127#ifdef CONFIG_DEBUG_MSM8960_UART
128 MSM_DEVICE(DEBUG_UART),
129#endif
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130};
131
132void __init msm_map_msm8960_io(void)
133{
134 iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
135}
136#endif /* CONFIG_ARCH_MSM8960 */
137
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138#ifdef CONFIG_ARCH_MSM7X30
139static struct map_desc msm7x30_io_desc[] __initdata = {
140 MSM_DEVICE(VIC),
8c27e6f3 141 MSM_CHIP_DEVICE(CSR, MSM7X30),
c83b2bf6 142 MSM_DEVICE(DMOV),
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143 MSM_CHIP_DEVICE(GPIO1, MSM7X30),
144 MSM_CHIP_DEVICE(GPIO2, MSM7X30),
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145 MSM_DEVICE(CLK_CTL),
146 MSM_DEVICE(CLK_CTL_SH2),
147 MSM_DEVICE(AD5),
148 MSM_DEVICE(MDC),
149 MSM_DEVICE(ACC),
150 MSM_DEVICE(SAW),
151 MSM_DEVICE(GCC),
152 MSM_DEVICE(TCSR),
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153#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
154 defined(CONFIG_DEBUG_MSM_UART3)
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155 MSM_DEVICE(DEBUG_UART),
156#endif
157 {
158 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
159 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
160 .length = MSM_SHARED_RAM_SIZE,
161 .type = MT_DEVICE,
162 },
163};
164
165void __init msm_map_msm7x30_io(void)
166{
167 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
168}
169#endif /* CONFIG_ARCH_MSM7X30 */
170
9b97173e 171void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
b12e9ba5 172 unsigned int mtype, void *caller)
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173{
174 if (mtype == MT_DEVICE) {
175 /* The peripherals in the 88000000 - D0000000 range
b595076a 176 * are only accessible by type MT_DEVICE_NONSHARED.
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177 * Adjust mtype as necessary to make this "just work."
178 */
179 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
180 mtype = MT_DEVICE_NONSHARED;
181 }
182
b12e9ba5 183 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
3042102a 184}
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