msm: Generalize timer register mappings
[deliverable/linux.git] / arch / arm / mach-msm / io.c
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1/* arch/arm/mach-msm/io.c
2 *
cf62ffae 3 * MSM7K, QSD io support
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4 *
5 * Copyright (C) 2007 Google, Inc.
8c27e6f3 6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
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7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
3042102a 23
a09e64fb 24#include <mach/hardware.h>
3042102a 25#include <asm/page.h>
a09e64fb 26#include <mach/msm_iomap.h>
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27#include <asm/mach/map.h>
28
a09e64fb 29#include <mach/board.h>
3042102a 30
8c27e6f3 31#define MSM_CHIP_DEVICE(name, chip) { \
bcc0f6af 32 .virtual = (unsigned long) MSM_##name##_BASE, \
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33 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
34 .length = chip##_##name##_SIZE, \
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35 .type = MT_DEVICE_NONSHARED, \
36 }
37
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38#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
39
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DW
40#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
41 || defined(CONFIG_ARCH_MSM7X25)
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42static struct map_desc msm_io_desc[] __initdata = {
43 MSM_DEVICE(VIC),
8c27e6f3 44 MSM_CHIP_DEVICE(CSR, MSM7X00),
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45 MSM_DEVICE(GPT),
46 MSM_DEVICE(DMOV),
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47 MSM_DEVICE(GPIO1),
48 MSM_DEVICE(GPIO2),
3042102a 49 MSM_DEVICE(CLK_CTL),
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50#ifdef CONFIG_MSM_DEBUG_UART
51 MSM_DEVICE(DEBUG_UART),
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52#endif
53#ifdef CONFIG_ARCH_MSM7X30
54 MSM_DEVICE(GCC),
6339f669 55#endif
3042102a 56 {
bcc0f6af 57 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
cf62ffae 58 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
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59 .length = MSM_SHARED_RAM_SIZE,
60 .type = MT_DEVICE,
61 },
62};
63
64void __init msm_map_common_io(void)
65{
66 /* Make sure the peripheral register window is closed, since
67 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
68 * pages are peripheral interface or not.
69 */
70 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
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71 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
72}
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73#endif
74
75#ifdef CONFIG_ARCH_QSD8X50
76static struct map_desc qsd8x50_io_desc[] __initdata = {
77 MSM_DEVICE(VIC),
8c27e6f3 78 MSM_CHIP_DEVICE(CSR, QSD8X50),
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79 MSM_DEVICE(DMOV),
80 MSM_DEVICE(GPIO1),
81 MSM_DEVICE(GPIO2),
82 MSM_DEVICE(CLK_CTL),
83 MSM_DEVICE(SIRC),
84 MSM_DEVICE(SCPLL),
85 MSM_DEVICE(AD5),
86 MSM_DEVICE(MDC),
87#ifdef CONFIG_MSM_DEBUG_UART
88 MSM_DEVICE(DEBUG_UART),
89#endif
90 {
91 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
92 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
93 .length = MSM_SHARED_RAM_SIZE,
94 .type = MT_DEVICE,
95 },
96};
97
98void __init msm_map_qsd8x50_io(void)
99{
100 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
101}
102#endif /* CONFIG_ARCH_QSD8X50 */
3042102a 103
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SM
104#ifdef CONFIG_ARCH_MSM8X60
105static struct map_desc msm8x60_io_desc[] __initdata = {
106 MSM_DEVICE(QGIC_DIST),
107 MSM_DEVICE(QGIC_CPU),
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108 MSM_CHIP_DEVICE(TMR, MSM8X60),
109 MSM_CHIP_DEVICE(TMR0, MSM8X60),
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110 MSM_DEVICE(ACC),
111 MSM_DEVICE(GCC),
112};
113
114void __init msm_map_msm8x60_io(void)
115{
116 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
117}
118#endif /* CONFIG_ARCH_MSM8X60 */
119
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120#ifdef CONFIG_ARCH_MSM7X30
121static struct map_desc msm7x30_io_desc[] __initdata = {
122 MSM_DEVICE(VIC),
8c27e6f3 123 MSM_CHIP_DEVICE(CSR, MSM7X30),
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124 MSM_DEVICE(DMOV),
125 MSM_DEVICE(GPIO1),
126 MSM_DEVICE(GPIO2),
127 MSM_DEVICE(CLK_CTL),
128 MSM_DEVICE(CLK_CTL_SH2),
129 MSM_DEVICE(AD5),
130 MSM_DEVICE(MDC),
131 MSM_DEVICE(ACC),
132 MSM_DEVICE(SAW),
133 MSM_DEVICE(GCC),
134 MSM_DEVICE(TCSR),
135#ifdef CONFIG_MSM_DEBUG_UART
136 MSM_DEVICE(DEBUG_UART),
137#endif
138 {
139 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
140 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
141 .length = MSM_SHARED_RAM_SIZE,
142 .type = MT_DEVICE,
143 },
144};
145
146void __init msm_map_msm7x30_io(void)
147{
148 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
149}
150#endif /* CONFIG_ARCH_MSM7X30 */
151
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152void __iomem *
153__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
154{
155 if (mtype == MT_DEVICE) {
156 /* The peripherals in the 88000000 - D0000000 range
b595076a 157 * are only accessible by type MT_DEVICE_NONSHARED.
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158 * Adjust mtype as necessary to make this "just work."
159 */
160 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
161 mtype = MT_DEVICE_NONSHARED;
162 }
163
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164 return __arm_ioremap_caller(phys_addr, size, mtype,
165 __builtin_return_address(0));
3042102a 166}
4916a108 167EXPORT_SYMBOL(__msm_ioremap);
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