Commit | Line | Data |
---|---|---|
3e4ea372 AH |
1 | /* linux/arch/arm/mach-msm/irq.c |
2 | * | |
3 | * Copyright (C) 2007 Google, Inc. | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ptrace.h> | |
21 | #include <linux/timer.h> | |
3e4ea372 | 22 | #include <linux/irq.h> |
fced80c7 | 23 | #include <linux/io.h> |
3e4ea372 | 24 | |
fced80c7 | 25 | #include <mach/hardware.h> |
3e4ea372 | 26 | |
a09e64fb | 27 | #include <mach/msm_iomap.h> |
3e4ea372 AH |
28 | |
29 | #define VIC_REG(off) (MSM_VIC_BASE + (off)) | |
30 | ||
31 | #define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */ | |
32 | #define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */ | |
33 | #define VIC_INT_EN0 VIC_REG(0x0010) | |
34 | #define VIC_INT_EN1 VIC_REG(0x0014) | |
35 | #define VIC_INT_ENCLEAR0 VIC_REG(0x0020) | |
36 | #define VIC_INT_ENCLEAR1 VIC_REG(0x0024) | |
37 | #define VIC_INT_ENSET0 VIC_REG(0x0030) | |
38 | #define VIC_INT_ENSET1 VIC_REG(0x0034) | |
39 | #define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */ | |
40 | #define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */ | |
41 | #define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */ | |
42 | #define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */ | |
43 | #define VIC_NO_PEND_VAL VIC_REG(0x0060) | |
44 | #define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */ | |
45 | #define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */ | |
46 | #define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */ | |
47 | #define VIC_IRQ_STATUS0 VIC_REG(0x0080) | |
48 | #define VIC_IRQ_STATUS1 VIC_REG(0x0084) | |
49 | #define VIC_FIQ_STATUS0 VIC_REG(0x0090) | |
50 | #define VIC_FIQ_STATUS1 VIC_REG(0x0094) | |
51 | #define VIC_RAW_STATUS0 VIC_REG(0x00A0) | |
52 | #define VIC_RAW_STATUS1 VIC_REG(0x00A4) | |
53 | #define VIC_INT_CLEAR0 VIC_REG(0x00B0) | |
54 | #define VIC_INT_CLEAR1 VIC_REG(0x00B4) | |
55 | #define VIC_SOFTINT0 VIC_REG(0x00C0) | |
56 | #define VIC_SOFTINT1 VIC_REG(0x00C4) | |
57 | #define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */ | |
58 | #define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */ | |
59 | #define VIC_IRQ_VEC_WR VIC_REG(0x00D8) | |
60 | #define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0) | |
61 | #define VIC_IRQ_IN_STACK VIC_REG(0x00E4) | |
62 | #define VIC_TEST_BUS_SEL VIC_REG(0x00E8) | |
63 | ||
64 | #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4)) | |
65 | #define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4)) | |
66 | ||
0f86ee08 | 67 | static void msm_irq_ack(struct irq_data *d) |
3e4ea372 | 68 | { |
0f86ee08 LB |
69 | void __iomem *reg = VIC_INT_CLEAR0 + ((d->irq & 32) ? 4 : 0); |
70 | writel(1 << (d->irq & 31), reg); | |
3e4ea372 AH |
71 | } |
72 | ||
0f86ee08 | 73 | static void msm_irq_mask(struct irq_data *d) |
3e4ea372 | 74 | { |
0f86ee08 LB |
75 | void __iomem *reg = VIC_INT_ENCLEAR0 + ((d->irq & 32) ? 4 : 0); |
76 | writel(1 << (d->irq & 31), reg); | |
3e4ea372 AH |
77 | } |
78 | ||
0f86ee08 | 79 | static void msm_irq_unmask(struct irq_data *d) |
3e4ea372 | 80 | { |
0f86ee08 LB |
81 | void __iomem *reg = VIC_INT_ENSET0 + ((d->irq & 32) ? 4 : 0); |
82 | writel(1 << (d->irq & 31), reg); | |
3e4ea372 AH |
83 | } |
84 | ||
0f86ee08 | 85 | static int msm_irq_set_wake(struct irq_data *d, unsigned int on) |
3e4ea372 AH |
86 | { |
87 | return -EINVAL; | |
88 | } | |
89 | ||
0f86ee08 | 90 | static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) |
3e4ea372 | 91 | { |
0f86ee08 LB |
92 | void __iomem *treg = VIC_INT_TYPE0 + ((d->irq & 32) ? 4 : 0); |
93 | void __iomem *preg = VIC_INT_POLARITY0 + ((d->irq & 32) ? 4 : 0); | |
94 | int b = 1 << (d->irq & 31); | |
3e4ea372 AH |
95 | |
96 | if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW)) | |
97 | writel(readl(preg) | b, preg); | |
98 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) | |
99 | writel(readl(preg) & (~b), preg); | |
100 | ||
101 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | |
102 | writel(readl(treg) | b, treg); | |
70c4fa22 | 103 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
3e4ea372 AH |
104 | } |
105 | if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { | |
106 | writel(readl(treg) & (~b), treg); | |
70c4fa22 | 107 | __irq_set_handler_locked(d->irq, handle_level_irq); |
3e4ea372 AH |
108 | } |
109 | return 0; | |
110 | } | |
111 | ||
112 | static struct irq_chip msm_irq_chip = { | |
0f86ee08 LB |
113 | .name = "msm", |
114 | .irq_ack = msm_irq_ack, | |
115 | .irq_mask = msm_irq_mask, | |
116 | .irq_unmask = msm_irq_unmask, | |
117 | .irq_set_wake = msm_irq_set_wake, | |
118 | .irq_set_type = msm_irq_set_type, | |
3e4ea372 AH |
119 | }; |
120 | ||
121 | void __init msm_init_irq(void) | |
122 | { | |
123 | unsigned n; | |
124 | ||
125 | /* select level interrupts */ | |
126 | writel(0, VIC_INT_TYPE0); | |
127 | writel(0, VIC_INT_TYPE1); | |
128 | ||
129 | /* select highlevel interrupts */ | |
130 | writel(0, VIC_INT_POLARITY0); | |
131 | writel(0, VIC_INT_POLARITY1); | |
132 | ||
133 | /* select IRQ for all INTs */ | |
134 | writel(0, VIC_INT_SELECT0); | |
135 | writel(0, VIC_INT_SELECT1); | |
136 | ||
137 | /* disable all INTs */ | |
138 | writel(0, VIC_INT_EN0); | |
139 | writel(0, VIC_INT_EN1); | |
140 | ||
141 | /* don't use 1136 vic */ | |
142 | writel(0, VIC_CONFIG); | |
143 | ||
144 | /* enable interrupt controller */ | |
145 | writel(1, VIC_INT_MASTEREN); | |
146 | ||
147 | for (n = 0; n < NR_MSM_IRQS; n++) { | |
f38c02f3 | 148 | irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); |
3e4ea372 AH |
149 | set_irq_flags(n, IRQF_VALID); |
150 | } | |
151 | } |