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e14411da JO |
1 | /* |
2 | * Copyright (C) 2002 ARM Ltd. | |
3 | * All Rights Reserved | |
4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/io.h> | |
18 | ||
19 | #include <asm/hardware/gic.h> | |
20 | #include <asm/cacheflush.h> | |
41ff445c | 21 | #include <asm/cputype.h> |
e14411da | 22 | #include <asm/mach-types.h> |
eb50439b | 23 | #include <asm/smp_plat.h> |
e14411da | 24 | |
e14411da | 25 | #include "scm-boot.h" |
be2109e1 | 26 | #include "common.h" |
e14411da JO |
27 | |
28 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 | |
29 | #define SCSS_CPU1CORE_RESET 0xD80 | |
30 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 | |
31 | ||
e14411da | 32 | extern void msm_secondary_startup(void); |
e14411da JO |
33 | |
34 | static DEFINE_SPINLOCK(boot_lock); | |
35 | ||
41ff445c JO |
36 | static inline int get_core_count(void) |
37 | { | |
38 | /* 1 + the PART[1:0] field of MIDR */ | |
39 | return ((read_cpuid_id() >> 4) & 3) + 1; | |
40 | } | |
41 | ||
44ea349f | 42 | static void __cpuinit msm_secondary_init(unsigned int cpu) |
e14411da | 43 | { |
e14411da JO |
44 | /* |
45 | * if any interrupts are already enabled for the primary | |
46 | * core (e.g. timer irq), then they will not have been enabled | |
47 | * for us: do so | |
48 | */ | |
49 | gic_secondary_init(0); | |
50 | ||
51 | /* | |
52 | * let the primary processor know we're out of the | |
53 | * pen, then head off into the C entry point | |
54 | */ | |
55 | pen_release = -1; | |
56 | smp_wmb(); | |
57 | ||
58 | /* | |
59 | * Synchronise with the boot thread. | |
60 | */ | |
61 | spin_lock(&boot_lock); | |
62 | spin_unlock(&boot_lock); | |
63 | } | |
64 | ||
65 | static __cpuinit void prepare_cold_cpu(unsigned int cpu) | |
66 | { | |
67 | int ret; | |
68 | ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), | |
69 | SCM_FLAG_COLDBOOT_CPU1); | |
70 | if (ret == 0) { | |
2b222a29 | 71 | void __iomem *sc1_base_ptr; |
e14411da JO |
72 | sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); |
73 | if (sc1_base_ptr) { | |
74 | writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); | |
75 | writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); | |
76 | writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); | |
77 | iounmap(sc1_base_ptr); | |
78 | } | |
79 | } else | |
80 | printk(KERN_DEBUG "Failed to set secondary core boot " | |
81 | "address\n"); | |
82 | } | |
83 | ||
44ea349f | 84 | static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle) |
e14411da JO |
85 | { |
86 | unsigned long timeout; | |
87 | static int cold_boot_done; | |
88 | ||
89 | /* Only need to bring cpu out of reset this way once */ | |
90 | if (cold_boot_done == false) { | |
91 | prepare_cold_cpu(cpu); | |
92 | cold_boot_done = true; | |
93 | } | |
94 | ||
95 | /* | |
96 | * set synchronisation state between this boot processor | |
97 | * and the secondary one | |
98 | */ | |
99 | spin_lock(&boot_lock); | |
100 | ||
101 | /* | |
102 | * The secondary processor is waiting to be released from | |
103 | * the holding pen - release it, then wait for it to flag | |
104 | * that it has been released by resetting pen_release. | |
105 | * | |
106 | * Note that "pen_release" is the hardware CPU ID, whereas | |
107 | * "cpu" is Linux's internal ID. | |
108 | */ | |
1d3cfb34 | 109 | pen_release = cpu_logical_map(cpu); |
e14411da JO |
110 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); |
111 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
112 | ||
113 | /* | |
114 | * Send the secondary CPU a soft interrupt, thereby causing | |
115 | * the boot monitor to read the system wide flags register, | |
116 | * and branch to the address found there. | |
117 | */ | |
ffae8940 | 118 | gic_raise_softirq(cpumask_of(cpu), 0); |
e14411da JO |
119 | |
120 | timeout = jiffies + (1 * HZ); | |
121 | while (time_before(jiffies, timeout)) { | |
122 | smp_rmb(); | |
123 | if (pen_release == -1) | |
124 | break; | |
125 | ||
126 | udelay(10); | |
127 | } | |
128 | ||
129 | /* | |
130 | * now the secondary core is starting up let it run its | |
131 | * calibrations, then wait for it to finish | |
132 | */ | |
133 | spin_unlock(&boot_lock); | |
134 | ||
135 | return pen_release != -1 ? -ENOSYS : 0; | |
136 | } | |
137 | ||
138 | /* | |
139 | * Initialise the CPU possible map early - this describes the CPUs | |
140 | * which may be present or become present in the system. The msm8x60 | |
141 | * does not support the ARM SCU, so just set the possible cpu mask to | |
142 | * NR_CPUS. | |
143 | */ | |
44ea349f | 144 | static void __init msm_smp_init_cpus(void) |
e14411da | 145 | { |
41ff445c | 146 | unsigned int i, ncores = get_core_count(); |
e14411da | 147 | |
a06f916b RK |
148 | if (ncores > nr_cpu_ids) { |
149 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
150 | ncores, nr_cpu_ids); | |
151 | ncores = nr_cpu_ids; | |
152 | } | |
153 | ||
41ff445c | 154 | for (i = 0; i < ncores; i++) |
e14411da | 155 | set_cpu_possible(i, true); |
0f7b332f RK |
156 | |
157 | set_smp_cross_call(gic_raise_softirq); | |
e14411da JO |
158 | } |
159 | ||
44ea349f | 160 | static void __init msm_smp_prepare_cpus(unsigned int max_cpus) |
e14411da | 161 | { |
e14411da | 162 | } |
44ea349f MZ |
163 | |
164 | struct smp_operations msm_smp_ops __initdata = { | |
165 | .smp_init_cpus = msm_smp_init_cpus, | |
166 | .smp_prepare_cpus = msm_smp_prepare_cpus, | |
167 | .smp_secondary_init = msm_secondary_init, | |
168 | .smp_boot_secondary = msm_boot_secondary, | |
169 | #ifdef CONFIG_HOTPLUG_CPU | |
170 | .cpu_die = msm_cpu_die, | |
171 | #endif | |
172 | }; |