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e14411da JO |
1 | /* |
2 | * Copyright (C) 2002 ARM Ltd. | |
3 | * All Rights Reserved | |
4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
e14411da JO |
15 | #include <linux/smp.h> |
16 | #include <linux/io.h> | |
17 | ||
41ff445c | 18 | #include <asm/cputype.h> |
eb50439b | 19 | #include <asm/smp_plat.h> |
e14411da | 20 | |
e14411da | 21 | #include "scm-boot.h" |
be2109e1 | 22 | #include "common.h" |
e14411da JO |
23 | |
24 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 | |
25 | #define SCSS_CPU1CORE_RESET 0xD80 | |
26 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 | |
27 | ||
52b52b46 | 28 | extern void secondary_startup(void); |
e14411da JO |
29 | |
30 | static DEFINE_SPINLOCK(boot_lock); | |
31 | ||
41ff445c JO |
32 | static inline int get_core_count(void) |
33 | { | |
34 | /* 1 + the PART[1:0] field of MIDR */ | |
35 | return ((read_cpuid_id() >> 4) & 3) + 1; | |
36 | } | |
37 | ||
8bd26e3a | 38 | static void msm_secondary_init(unsigned int cpu) |
e14411da | 39 | { |
e14411da JO |
40 | /* |
41 | * Synchronise with the boot thread. | |
42 | */ | |
43 | spin_lock(&boot_lock); | |
44 | spin_unlock(&boot_lock); | |
45 | } | |
46 | ||
8bd26e3a | 47 | static void prepare_cold_cpu(unsigned int cpu) |
e14411da JO |
48 | { |
49 | int ret; | |
52b52b46 | 50 | ret = scm_set_boot_addr(virt_to_phys(secondary_startup), |
e14411da JO |
51 | SCM_FLAG_COLDBOOT_CPU1); |
52 | if (ret == 0) { | |
2b222a29 | 53 | void __iomem *sc1_base_ptr; |
e14411da JO |
54 | sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); |
55 | if (sc1_base_ptr) { | |
56 | writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); | |
57 | writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); | |
58 | writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); | |
59 | iounmap(sc1_base_ptr); | |
60 | } | |
61 | } else | |
62 | printk(KERN_DEBUG "Failed to set secondary core boot " | |
63 | "address\n"); | |
64 | } | |
65 | ||
8bd26e3a | 66 | static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) |
e14411da | 67 | { |
e14411da JO |
68 | static int cold_boot_done; |
69 | ||
70 | /* Only need to bring cpu out of reset this way once */ | |
71 | if (cold_boot_done == false) { | |
72 | prepare_cold_cpu(cpu); | |
73 | cold_boot_done = true; | |
74 | } | |
75 | ||
76 | /* | |
77 | * set synchronisation state between this boot processor | |
78 | * and the secondary one | |
79 | */ | |
80 | spin_lock(&boot_lock); | |
81 | ||
e14411da JO |
82 | /* |
83 | * Send the secondary CPU a soft interrupt, thereby causing | |
84 | * the boot monitor to read the system wide flags register, | |
85 | * and branch to the address found there. | |
86 | */ | |
b1cffebf | 87 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
e14411da | 88 | |
e14411da JO |
89 | /* |
90 | * now the secondary core is starting up let it run its | |
91 | * calibrations, then wait for it to finish | |
92 | */ | |
93 | spin_unlock(&boot_lock); | |
94 | ||
52b52b46 | 95 | return 0; |
e14411da JO |
96 | } |
97 | ||
98 | /* | |
99 | * Initialise the CPU possible map early - this describes the CPUs | |
100 | * which may be present or become present in the system. The msm8x60 | |
101 | * does not support the ARM SCU, so just set the possible cpu mask to | |
102 | * NR_CPUS. | |
103 | */ | |
44ea349f | 104 | static void __init msm_smp_init_cpus(void) |
e14411da | 105 | { |
41ff445c | 106 | unsigned int i, ncores = get_core_count(); |
e14411da | 107 | |
a06f916b RK |
108 | if (ncores > nr_cpu_ids) { |
109 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
110 | ncores, nr_cpu_ids); | |
111 | ncores = nr_cpu_ids; | |
112 | } | |
113 | ||
41ff445c | 114 | for (i = 0; i < ncores; i++) |
e14411da JO |
115 | set_cpu_possible(i, true); |
116 | } | |
117 | ||
44ea349f | 118 | static void __init msm_smp_prepare_cpus(unsigned int max_cpus) |
e14411da | 119 | { |
e14411da | 120 | } |
44ea349f MZ |
121 | |
122 | struct smp_operations msm_smp_ops __initdata = { | |
123 | .smp_init_cpus = msm_smp_init_cpus, | |
124 | .smp_prepare_cpus = msm_smp_prepare_cpus, | |
125 | .smp_secondary_init = msm_secondary_init, | |
126 | .smp_boot_secondary = msm_boot_secondary, | |
127 | #ifdef CONFIG_HOTPLUG_CPU | |
128 | .cpu_die = msm_cpu_die, | |
129 | #endif | |
130 | }; |