[deliverable/linux.git] / arch / arm / mach-msm / smd_private.h

/* arch/arm/mach-msm/smd_private.h
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2007 QUALCOMM Incorporated
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_

#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/list.h>

struct smem_heap_info
{
	unsigned initialized;
	unsigned free_offset;
	unsigned heap_remaining;
	unsigned reserved;
};

struct smem_heap_entry
{
	unsigned allocated;
	unsigned offset;
	unsigned size;
	unsigned reserved;
};

struct smem_proc_comm
{
	unsigned command;
	unsigned status;
	unsigned data1;
	unsigned data2;
};

#define PC_APPS  0
#define PC_MODEM 1

#define VERSION_SMD       0
#define VERSION_QDSP6     4
#define VERSION_APPS_SBL  6
#define VERSION_MODEM_SBL 7
#define VERSION_APPS      8
#define VERSION_MODEM     9

struct smem_shared
{
	struct smem_proc_comm proc_comm[4];
	unsigned version[32];
	struct smem_heap_info heap_info;
	struct smem_heap_entry heap_toc[512];
};

#define SMSM_V1_SIZE		(sizeof(unsigned) * 8)
#define SMSM_V2_SIZE		(sizeof(unsigned) * 4)

#ifndef CONFIG_ARCH_MSM_SCORPION
struct smsm_interrupt_info
{
	uint32_t interrupt_mask;
	uint32_t pending_interrupts;
	uint32_t wakeup_reason;
};
#else
#define DEM_MAX_PORT_NAME_LEN (20)
struct msm_dem_slave_data {
	uint32_t sleep_time;
	uint32_t interrupt_mask;
	uint32_t resources_used;
	uint32_t reserved1;

	uint32_t wakeup_reason;
	uint32_t pending_interrupts;
	uint32_t rpc_prog;
	uint32_t rpc_proc;
	char     smd_port_name[DEM_MAX_PORT_NAME_LEN];
	uint32_t reserved2;
};
#endif

#define SZ_DIAG_ERR_MSG 0xC8
#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL

#define SMSM_INIT		0x00000001
#define SMSM_SMDINIT		0x00000008
#define SMSM_RPCINIT		0x00000020
#define SMSM_RESET		0x00000040
#define SMSM_RSA		0x00000080
#define SMSM_RUN		0x00000100
#define SMSM_PWRC		0x00000200
#define SMSM_TIMEWAIT		0x00000400
#define SMSM_TIMEINIT		0x00000800
#define SMSM_PWRC_EARLY_EXIT	0x00001000
#define SMSM_WFPI		0x00002000
#define SMSM_SLEEP		0x00004000
#define SMSM_SLEEPEXIT		0x00008000
#define SMSM_APPS_REBOOT	0x00020000
#define SMSM_SYSTEM_POWER_DOWN	0x00040000
#define SMSM_SYSTEM_REBOOT	0x00080000
#define SMSM_SYSTEM_DOWNLOAD	0x00100000
#define SMSM_PWRC_SUSPEND	0x00200000
#define SMSM_APPS_SHUTDOWN	0x00400000
#define SMSM_SMD_LOOPBACK	0x00800000
#define SMSM_RUN_QUIET		0x01000000
#define SMSM_MODEM_WAIT		0x02000000
#define SMSM_MODEM_BREAK	0x04000000
#define SMSM_MODEM_CONTINUE	0x08000000
#define SMSM_UNKNOWN		0x80000000

#define SMSM_WKUP_REASON_RPC	0x00000001
#define SMSM_WKUP_REASON_INT	0x00000002
#define SMSM_WKUP_REASON_GPIO	0x00000004
#define SMSM_WKUP_REASON_TIMER	0x00000008
#define SMSM_WKUP_REASON_ALARM	0x00000010
#define SMSM_WKUP_REASON_RESET	0x00000020

#ifndef CONFIG_ARCH_MSM_SCORPION
enum smsm_state_item {
	SMSM_STATE_APPS = 1,
	SMSM_STATE_MODEM = 3,
	SMSM_STATE_COUNT,
};
#else
enum smsm_state_item {
	SMSM_STATE_APPS,
	SMSM_STATE_MODEM,
	SMSM_STATE_HEXAGON,
	SMSM_STATE_APPS_DEM,
	SMSM_STATE_MODEM_DEM,
	SMSM_STATE_QDSP6_DEM,
	SMSM_STATE_POWER_MASTER_DEM,
	SMSM_STATE_TIME_MASTER_DEM,
	SMSM_STATE_COUNT,
};
#endif

void *smem_alloc(unsigned id, unsigned size);
int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
uint32_t smsm_get_state(enum smsm_state_item item);
int smsm_set_sleep_duration(uint32_t delay);
void smsm_print_sleep_info(void);

#define SMEM_NUM_SMD_CHANNELS        64

typedef enum
{
	/* fixed items */
	SMEM_PROC_COMM = 0,
	SMEM_HEAP_INFO,
	SMEM_ALLOCATION_TABLE,
	SMEM_VERSION_INFO,
	SMEM_HW_RESET_DETECT,
	SMEM_AARM_WARM_BOOT,
	SMEM_DIAG_ERR_MESSAGE,
	SMEM_SPINLOCK_ARRAY,
	SMEM_MEMORY_BARRIER_LOCATION,

	/* dynamic items */
	SMEM_AARM_PARTITION_TABLE,
	SMEM_AARM_BAD_BLOCK_TABLE,
	SMEM_RESERVE_BAD_BLOCKS,
	SMEM_WM_UUID,
	SMEM_CHANNEL_ALLOC_TBL,
	SMEM_SMD_BASE_ID,
	SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
	SMEM_SMEM_LOG_EVENTS,
	SMEM_SMEM_STATIC_LOG_IDX,
	SMEM_SMEM_STATIC_LOG_EVENTS,
	SMEM_SMEM_SLOW_CLOCK_SYNC,
	SMEM_SMEM_SLOW_CLOCK_VALUE,
	SMEM_BIO_LED_BUF,
	SMEM_SMSM_SHARED_STATE,
	SMEM_SMSM_INT_INFO,
	SMEM_SMSM_SLEEP_DELAY,
	SMEM_SMSM_LIMIT_SLEEP,
	SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
	SMEM_KEYPAD_KEYS_PRESSED,
	SMEM_KEYPAD_STATE_UPDATED,
	SMEM_KEYPAD_STATE_IDX,
	SMEM_GPIO_INT,
	SMEM_MDDI_LCD_IDX,
	SMEM_MDDI_HOST_DRIVER_STATE,
	SMEM_MDDI_LCD_DISP_STATE,
	SMEM_LCD_CUR_PANEL,
	SMEM_MARM_BOOT_SEGMENT_INFO,
	SMEM_AARM_BOOT_SEGMENT_INFO,
	SMEM_SLEEP_STATIC,
	SMEM_SCORPION_FREQUENCY,
	SMEM_SMD_PROFILES,
	SMEM_TSSC_BUSY,
	SMEM_HS_SUSPEND_FILTER_INFO,
	SMEM_BATT_INFO,
	SMEM_APPS_BOOT_MODE,
	SMEM_VERSION_FIRST,
	SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
	SMEM_OSS_RRCASN1_BUF1,
	SMEM_OSS_RRCASN1_BUF2,
	SMEM_ID_VENDOR0,
	SMEM_ID_VENDOR1,
	SMEM_ID_VENDOR2,
	SMEM_HW_SW_BUILD_ID,
	SMEM_SMD_BLOCK_PORT_BASE_ID,
	SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
	SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
	SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
	SMEM_SCLK_CONVERSION,
	SMEM_SMD_SMSM_INTR_MUX,
	SMEM_SMSM_CPU_INTR_MASK,
	SMEM_APPS_DEM_SLAVE_DATA,
	SMEM_QDSP6_DEM_SLAVE_DATA,
	SMEM_CLKREGIM_BSP,
	SMEM_CLKREGIM_SOURCES,
	SMEM_SMD_FIFO_BASE_ID,
	SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
	SMEM_POWER_ON_STATUS_INFO,
	SMEM_DAL_AREA,
	SMEM_SMEM_LOG_POWER_IDX,
	SMEM_SMEM_LOG_POWER_WRAP,
	SMEM_SMEM_LOG_POWER_EVENTS,
	SMEM_ERR_CRASH_LOG,
	SMEM_ERR_F3_TRACE_LOG,	
	SMEM_NUM_ITEMS,
} smem_mem_type;


#define SMD_SS_CLOSED		0x00000000
#define SMD_SS_OPENING		0x00000001
#define SMD_SS_OPENED		0x00000002
#define SMD_SS_FLUSHING		0x00000003
#define SMD_SS_CLOSING		0x00000004
#define SMD_SS_RESET		0x00000005
#define SMD_SS_RESET_OPENING	0x00000006

#define SMD_BUF_SIZE		8192
#define SMD_CHANNELS		64

#define SMD_HEADER_SIZE		20

struct smd_alloc_elm {
	char name[20];
	uint32_t cid;
	uint32_t ctype;
	uint32_t ref_count;
};

struct smd_half_channel {
	unsigned state;
	unsigned char fDSR;
	unsigned char fCTS;
	unsigned char fCD;
	unsigned char fRI;
	unsigned char fHEAD;
	unsigned char fTAIL;
	unsigned char fSTATE;
	unsigned char fUNUSED;
	unsigned tail;
	unsigned head;
} __attribute__((packed));

struct smd_shared_v1 {
	struct smd_half_channel ch0;
	unsigned char data0[SMD_BUF_SIZE];
	struct smd_half_channel ch1;
	unsigned char data1[SMD_BUF_SIZE];
};

struct smd_shared_v2 {
	struct smd_half_channel ch0;
	struct smd_half_channel ch1;
};	

struct smd_channel {
	volatile struct smd_half_channel *send;
	volatile struct smd_half_channel *recv;
	unsigned char *send_data;
	unsigned char *recv_data;

	unsigned fifo_mask;
	unsigned fifo_size;
	unsigned current_packet;
	unsigned n;

	struct list_head ch_list;

	void *priv;
	void (*notify)(void *priv, unsigned flags);

	int (*read)(struct smd_channel *ch, void *data, int len);
	int (*write)(struct smd_channel *ch, const void *data, int len);
	int (*read_avail)(struct smd_channel *ch);
	int (*write_avail)(struct smd_channel *ch);

	void (*update_state)(struct smd_channel *ch);
	unsigned last_state;
	void (*notify_other_cpu)(void);
	unsigned type;

	char name[32];
	struct platform_device pdev;
};

#define SMD_TYPE_MASK		0x0FF
#define SMD_TYPE_APPS_MODEM	0x000
#define SMD_TYPE_APPS_DSP	0x001
#define SMD_TYPE_MODEM_DSP	0x002

#define SMD_KIND_MASK		0xF00
#define SMD_KIND_UNKNOWN	0x000
#define SMD_KIND_STREAM		0x100
#define SMD_KIND_PACKET		0x200

extern struct list_head smd_ch_closed_list;
extern struct list_head smd_ch_list_modem;
extern struct list_head smd_ch_list_dsp;

extern spinlock_t smd_lock;
extern spinlock_t smem_lock;

void *smem_find(unsigned id, unsigned size);
void *smem_item(unsigned id, unsigned *size);
uint32_t raw_smsm_get_state(enum smsm_state_item item);

#endif
Commit	Line	Data
2eb44eb9 BS	1	/* arch/arm/mach-msm/smd_private.h
	2	*
	3	* Copyright (C) 2007 Google, Inc.
	4	* Copyright (c) 2007 QUALCOMM Incorporated
	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16	#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
	17	#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
	18
03e00cd3 BS	19	#include <linux/platform_device.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/list.h>
	22
2eb44eb9 BS	23	struct smem_heap_info
	24	{
	25	unsigned initialized;
	26	unsigned free_offset;
	27	unsigned heap_remaining;
	28	unsigned reserved;
	29	};
	30
	31	struct smem_heap_entry
	32	{
	33	unsigned allocated;
	34	unsigned offset;
	35	unsigned size;
	36	unsigned reserved;
	37	};
	38
	39	struct smem_proc_comm
	40	{
	41	unsigned command;
	42	unsigned status;
	43	unsigned data1;
	44	unsigned data2;
	45	};
	46
	47	#define PC_APPS 0
	48	#define PC_MODEM 1
	49
5b0f5a3f	50	#define VERSION_SMD 0
2eb44eb9 BS	51	#define VERSION_QDSP6 4
	52	#define VERSION_APPS_SBL 6
	53	#define VERSION_MODEM_SBL 7
	54	#define VERSION_APPS 8
	55	#define VERSION_MODEM 9
	56
	57	struct smem_shared
	58	{
	59	struct smem_proc_comm proc_comm[4];
	60	unsigned version[32];
	61	struct smem_heap_info heap_info;
5b0f5a3f	62	struct smem_heap_entry heap_toc[512];
2eb44eb9 BS	63	};
2eb44eb9 BS	64
5b0f5a3f	65	#define SMSM_V1_SIZE (sizeof(unsigned) * 8)
5b0f5a3f	66	#define SMSM_V2_SIZE (sizeof(unsigned) * 4)
2eb44eb9	67
ec9d3d14	68	#ifndef CONFIG_ARCH_MSM_SCORPION
2eb44eb9 BS	69	struct smsm_interrupt_info
2eb44eb9 BS	70	{
ec9d3d14 AH	71	uint32_t interrupt_mask;
	72	uint32_t pending_interrupts;
	73	uint32_t wakeup_reason;
2eb44eb9	74	};
ec9d3d14 AH	75	#else
	76	#define DEM_MAX_PORT_NAME_LEN (20)
	77	struct msm_dem_slave_data {
	78	uint32_t sleep_time;
	79	uint32_t interrupt_mask;
	80	uint32_t resources_used;
	81	uint32_t reserved1;
	82
	83	uint32_t wakeup_reason;
	84	uint32_t pending_interrupts;
	85	uint32_t rpc_prog;
	86	uint32_t rpc_proc;
	87	char smd_port_name[DEM_MAX_PORT_NAME_LEN];
	88	uint32_t reserved2;
	89	};
	90	#endif
2eb44eb9 BS	91
	92	#define SZ_DIAG_ERR_MSG 0xC8
	93	#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
	94	#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
	95	#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
	96	#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
	97
5b0f5a3f BS	98	#define SMSM_INIT 0x00000001
	99	#define SMSM_SMDINIT 0x00000008
	100	#define SMSM_RPCINIT 0x00000020
	101	#define SMSM_RESET 0x00000040
	102	#define SMSM_RSA 0x00000080
	103	#define SMSM_RUN 0x00000100
	104	#define SMSM_PWRC 0x00000200
	105	#define SMSM_TIMEWAIT 0x00000400
	106	#define SMSM_TIMEINIT 0x00000800
	107	#define SMSM_PWRC_EARLY_EXIT 0x00001000
	108	#define SMSM_WFPI 0x00002000
	109	#define SMSM_SLEEP 0x00004000
	110	#define SMSM_SLEEPEXIT 0x00008000
	111	#define SMSM_APPS_REBOOT 0x00020000
	112	#define SMSM_SYSTEM_POWER_DOWN 0x00040000
	113	#define SMSM_SYSTEM_REBOOT 0x00080000
	114	#define SMSM_SYSTEM_DOWNLOAD 0x00100000
	115	#define SMSM_PWRC_SUSPEND 0x00200000
	116	#define SMSM_APPS_SHUTDOWN 0x00400000
	117	#define SMSM_SMD_LOOPBACK 0x00800000
	118	#define SMSM_RUN_QUIET 0x01000000
	119	#define SMSM_MODEM_WAIT 0x02000000
	120	#define SMSM_MODEM_BREAK 0x04000000
	121	#define SMSM_MODEM_CONTINUE 0x08000000
	122	#define SMSM_UNKNOWN 0x80000000
2eb44eb9 BS	123
	124	#define SMSM_WKUP_REASON_RPC 0x00000001
	125	#define SMSM_WKUP_REASON_INT 0x00000002
	126	#define SMSM_WKUP_REASON_GPIO 0x00000004
	127	#define SMSM_WKUP_REASON_TIMER 0x00000008
	128	#define SMSM_WKUP_REASON_ALARM 0x00000010
	129	#define SMSM_WKUP_REASON_RESET 0x00000020
	130
28379410 AH	131	#ifndef CONFIG_ARCH_MSM_SCORPION
	132	enum smsm_state_item {
	133	SMSM_STATE_APPS = 1,
	134	SMSM_STATE_MODEM = 3,
	135	SMSM_STATE_COUNT,
	136	};
	137	#else
	138	enum smsm_state_item {
	139	SMSM_STATE_APPS,
	140	SMSM_STATE_MODEM,
	141	SMSM_STATE_HEXAGON,
	142	SMSM_STATE_APPS_DEM,
	143	SMSM_STATE_MODEM_DEM,
	144	SMSM_STATE_QDSP6_DEM,
	145	SMSM_STATE_POWER_MASTER_DEM,
	146	SMSM_STATE_TIME_MASTER_DEM,
	147	SMSM_STATE_COUNT,
	148	};
	149	#endif
	150
2eb44eb9	151	void *smem_alloc(unsigned id, unsigned size);
28379410 AH	152	int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
28379410 AH	153	uint32_t smsm_get_state(enum smsm_state_item item);
2eb44eb9	154	int smsm_set_sleep_duration(uint32_t delay);
2eb44eb9 BS	155	void smsm_print_sleep_info(void);
	156
	157	#define SMEM_NUM_SMD_CHANNELS 64
	158
	159	typedef enum
	160	{
	161	/* fixed items */
	162	SMEM_PROC_COMM = 0,
	163	SMEM_HEAP_INFO,
	164	SMEM_ALLOCATION_TABLE,
	165	SMEM_VERSION_INFO,
	166	SMEM_HW_RESET_DETECT,
	167	SMEM_AARM_WARM_BOOT,
	168	SMEM_DIAG_ERR_MESSAGE,
	169	SMEM_SPINLOCK_ARRAY,
	170	SMEM_MEMORY_BARRIER_LOCATION,
	171
	172	/* dynamic items */
	173	SMEM_AARM_PARTITION_TABLE,
	174	SMEM_AARM_BAD_BLOCK_TABLE,
	175	SMEM_RESERVE_BAD_BLOCKS,
	176	SMEM_WM_UUID,
	177	SMEM_CHANNEL_ALLOC_TBL,
	178	SMEM_SMD_BASE_ID,
	179	SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
	180	SMEM_SMEM_LOG_EVENTS,
	181	SMEM_SMEM_STATIC_LOG_IDX,
	182	SMEM_SMEM_STATIC_LOG_EVENTS,
	183	SMEM_SMEM_SLOW_CLOCK_SYNC,
	184	SMEM_SMEM_SLOW_CLOCK_VALUE,
	185	SMEM_BIO_LED_BUF,
	186	SMEM_SMSM_SHARED_STATE,
	187	SMEM_SMSM_INT_INFO,
	188	SMEM_SMSM_SLEEP_DELAY,
	189	SMEM_SMSM_LIMIT_SLEEP,
	190	SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
	191	SMEM_KEYPAD_KEYS_PRESSED,
	192	SMEM_KEYPAD_STATE_UPDATED,
	193	SMEM_KEYPAD_STATE_IDX,
	194	SMEM_GPIO_INT,
	195	SMEM_MDDI_LCD_IDX,
	196	SMEM_MDDI_HOST_DRIVER_STATE,
	197	SMEM_MDDI_LCD_DISP_STATE,
	198	SMEM_LCD_CUR_PANEL,
	199	SMEM_MARM_BOOT_SEGMENT_INFO,
	200	SMEM_AARM_BOOT_SEGMENT_INFO,
	201	SMEM_SLEEP_STATIC,
	202	SMEM_SCORPION_FREQUENCY,
	203	SMEM_SMD_PROFILES,
	204	SMEM_TSSC_BUSY,
	205	SMEM_HS_SUSPEND_FILTER_INFO,
	206	SMEM_BATT_INFO,
	207	SMEM_APPS_BOOT_MODE,
	208	SMEM_VERSION_FIRST,
	209	SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
	210	SMEM_OSS_RRCASN1_BUF1,
	211	SMEM_OSS_RRCASN1_BUF2,
	212	SMEM_ID_VENDOR0,
	213	SMEM_ID_VENDOR1,
	214	SMEM_ID_VENDOR2,
	215	SMEM_HW_SW_BUILD_ID,
5b0f5a3f BS	216	SMEM_SMD_BLOCK_PORT_BASE_ID,
	217	SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
	218	SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
	219	SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
	220	SMEM_SCLK_CONVERSION,
	221	SMEM_SMD_SMSM_INTR_MUX,
	222	SMEM_SMSM_CPU_INTR_MASK,
	223	SMEM_APPS_DEM_SLAVE_DATA,
	224	SMEM_QDSP6_DEM_SLAVE_DATA,
	225	SMEM_CLKREGIM_BSP,
	226	SMEM_CLKREGIM_SOURCES,
	227	SMEM_SMD_FIFO_BASE_ID,
	228	SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
	229	SMEM_POWER_ON_STATUS_INFO,
	230	SMEM_DAL_AREA,
	231	SMEM_SMEM_LOG_POWER_IDX,
	232	SMEM_SMEM_LOG_POWER_WRAP,
	233	SMEM_SMEM_LOG_POWER_EVENTS,
	234	SMEM_ERR_CRASH_LOG,
	235	SMEM_ERR_F3_TRACE_LOG,
2eb44eb9 BS	236	SMEM_NUM_ITEMS,
	237	} smem_mem_type;
	238
03e00cd3 BS	239
	240	#define SMD_SS_CLOSED 0x00000000
	241	#define SMD_SS_OPENING 0x00000001
	242	#define SMD_SS_OPENED 0x00000002
	243	#define SMD_SS_FLUSHING 0x00000003
	244	#define SMD_SS_CLOSING 0x00000004
	245	#define SMD_SS_RESET 0x00000005
	246	#define SMD_SS_RESET_OPENING 0x00000006
	247
	248	#define SMD_BUF_SIZE 8192
	249	#define SMD_CHANNELS 64
	250
	251	#define SMD_HEADER_SIZE 20
	252
	253	struct smd_alloc_elm {
	254	char name[20];
	255	uint32_t cid;
	256	uint32_t ctype;
	257	uint32_t ref_count;
	258	};
	259
	260	struct smd_half_channel {
	261	unsigned state;
	262	unsigned char fDSR;
	263	unsigned char fCTS;
	264	unsigned char fCD;
	265	unsigned char fRI;
	266	unsigned char fHEAD;
	267	unsigned char fTAIL;
	268	unsigned char fSTATE;
	269	unsigned char fUNUSED;
	270	unsigned tail;
	271	unsigned head;
	272	} __attribute__((packed));
	273
	274	struct smd_shared_v1 {
	275	struct smd_half_channel ch0;
	276	unsigned char data0[SMD_BUF_SIZE];
	277	struct smd_half_channel ch1;
	278	unsigned char data1[SMD_BUF_SIZE];
	279	};
	280
	281	struct smd_shared_v2 {
	282	struct smd_half_channel ch0;
	283	struct smd_half_channel ch1;
	284	};
	285
	286	struct smd_channel {
	287	volatile struct smd_half_channel *send;
	288	volatile struct smd_half_channel *recv;
	289	unsigned char *send_data;
	290	unsigned char *recv_data;
	291
	292	unsigned fifo_mask;
	293	unsigned fifo_size;
	294	unsigned current_packet;
	295	unsigned n;
	296
	297	struct list_head ch_list;
	298
	299	void *priv;
	300	void (notify)(void priv, unsigned flags);
	301
	302	int (read)(struct smd_channel ch, void *data, int len);
303	int (write)(struct smd_channel ch, const void *data, int len);
304	int (read_avail)(struct smd_channel ch);
305	int (write_avail)(struct smd_channel ch);
306
307	void (update_state)(struct smd_channel ch);
308	unsigned last_state;
309	void (*notify_other_cpu)(void);
310	unsigned type;
311
312	char name[32];
313	struct platform_device pdev;
314	};
315
316	#define SMD_TYPE_MASK 0x0FF
317	#define SMD_TYPE_APPS_MODEM 0x000
318	#define SMD_TYPE_APPS_DSP 0x001
319	#define SMD_TYPE_MODEM_DSP 0x002
320
321	#define SMD_KIND_MASK 0xF00
322	#define SMD_KIND_UNKNOWN 0x000
323	#define SMD_KIND_STREAM 0x100
324	#define SMD_KIND_PACKET 0x200
325
326	extern struct list_head smd_ch_closed_list;
37521a31 BS	327	extern struct list_head smd_ch_list_modem;
37521a31 BS	328	extern struct list_head smd_ch_list_dsp;
03e00cd3 BS	329
	330	extern spinlock_t smd_lock;
	331	extern spinlock_t smem_lock;
	332
	333	void *smem_find(unsigned id, unsigned size);
	334	void smem_item(unsigned id, unsigned size);
	335	uint32_t raw_smsm_get_state(enum smsm_state_item item);
	336
2eb44eb9	337	#endif