[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/mach/time.h>
#include <asm/localtimer.h>

#include "common.h"

#define TIMER_MATCH_VAL			0x0000
#define TIMER_COUNT_VAL			0x0004
#define TIMER_ENABLE			0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
#define TIMER_ENABLE_EN			BIT(0)
#define TIMER_CLEAR			0x000C
#define DGT_CLK_CTL			0x10
#define DGT_CLK_CTL_DIV_4		0x3
#define TIMER_STS_GPT0_CLR_PEND		BIT(10)

#define GPT_HZ 32768

#define MSM_DGT_SHIFT 5

static void __iomem *event_base;
static void __iomem *sts_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	ctrl &= ~TIMER_ENABLE_EN;
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);

	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);

	if (sts_base)
		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
			cpu_relax();

	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}

static struct clock_event_device msm_clockevent = {
	.name		= "gp_timer",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= msm_timer_set_next_event,
	.set_mode	= msm_timer_set_mode,
};

static union {
	struct clock_event_device *evt;
	struct clock_event_device * __percpu *percpu_evt;
} msm_evt;

static void __iomem *source_base;

static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

#ifdef CONFIG_LOCAL_TIMERS
static int msm_local_timer_setup(struct clock_event_device *evt)
{
	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	evt->irq = msm_clockevent.irq;
	evt->name = "local_timer";
	evt->features = msm_clockevent.features;
	evt->rating = msm_clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;

	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void msm_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}

static struct local_timer_ops msm_local_timer_ops = {
	.setup	= msm_local_timer_setup,
	.stop	= msm_local_timer_stop,
};
#endif /* CONFIG_LOCAL_TIMERS */

static notrace u32 msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clock_event_device *ce = &msm_clockevent;
	struct clocksource *cs = &msm_clocksource;
	int res;

	ce->cpumask = cpumask_of(0);
	ce->irq = irq;

	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
	if (percpu) {
		msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
		if (!msm_evt.percpu_evt) {
			pr_err("memory allocation failed for %s\n", ce->name);
			goto err;
		}
		*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
					 ce->name, msm_evt.percpu_evt);
		if (!res) {
			enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_LOCAL_TIMERS
			local_timer_register(&msm_local_timer_ops);
#endif
		}
	} else {
		msm_evt.evt = ce;
		res = request_irq(ce->irq, msm_timer_interrupt,
				  IRQF_TIMER | IRQF_NOBALANCING |
				  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
	}

	if (res)
		pr_err("request_irq failed for %s\n", ce->name);
err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
}

#ifdef CONFIG_OF
static const struct of_device_id msm_timer_match[] __initconst = {
	{ .compatible = "qcom,kpss-timer" },
	{ .compatible = "qcom,scss-timer" },
	{ },
};

void __init msm_dt_timer_init(void)
{
	struct device_node *np;
	u32 freq;
	int irq;
	struct resource res;
	u32 percpu_offset;
	void __iomem *base;
	void __iomem *cpu0_base;

	np = of_find_matching_node(NULL, msm_timer_match);
	if (!np) {
		pr_err("Can't find msm timer DT node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to map event base\n");
		return;
	}

	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return;
	}

	/* We use CPU0's DGT for the clocksource */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("Failed to parse DGT resource\n");
		return;
	}

	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
		pr_err("Failed to map source base\n");
		return;
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return;
	}
	of_node_put(np);

	event_base = base + 0x4;
	sts_base = base + 0x88;
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

	msm_timer_init(freq, 32, irq, !!percpu_offset);
}
#endif

static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
				u32 sts)
{
	void __iomem *base;

	base = ioremap(addr, SZ_256);
	if (!base) {
		pr_err("Failed to map timer base\n");
		return -ENOMEM;
	}
	event_base = base + event;
	source_base = base + source;
	if (sts)
		sts_base = base + sts;

	return 0;
}

void __init msm7x01_timer_init(void)
{
	struct clocksource *cs = &msm_clocksource;

	if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
		return;
	cs->read = msm_read_timer_count_shift;
	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	/* 600 KHz */
	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
			false);
}

void __init msm7x30_timer_init(void)
{
	if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
		return;
	msm_timer_init(24576000 / 4, 32, 1, false);
}

void __init qsd8x50_timer_init(void)
{
	if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
		return;
	msm_timer_init(19200000 / 4, 32, 7, false);
}
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
4312a7ef	4	* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
3e4ea372	19	#include <linux/init.h>
3e4ea372 AH	20	#include <linux/interrupt.h>
3e4ea372 AH	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
6e332163 SB	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
38ff87f7	26	#include <linux/sched_clock.h>
3e4ea372 AH	27
3e4ea372 AH	28	#include <asm/mach/time.h>
4a184075	29	#include <asm/localtimer.h>
ebf30dc9	30
4312a7ef	31	#include "common.h"
3e4ea372	32
e25e3d1f SB	33	#define TIMER_MATCH_VAL 0x0000
	34	#define TIMER_COUNT_VAL 0x0004
	35	#define TIMER_ENABLE 0x0008
	36	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
	37	#define TIMER_ENABLE_EN BIT(0)
	38	#define TIMER_CLEAR 0x000C
	39	#define DGT_CLK_CTL 0x10
	40	#define DGT_CLK_CTL_DIV_4 0x3
	41	#define TIMER_STS_GPT0_CLR_PEND BIT(10)
3e4ea372 AH	42
3e4ea372 AH	43	#define GPT_HZ 32768
672039f0	44
2081a6b5	45	#define MSM_DGT_SHIFT 5
3e4ea372	46
2a00c106	47	static void __iomem *event_base;
e25e3d1f	48	static void __iomem *sts_base;
a850c3f6	49
3e4ea372 AH	50	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	51	{
28af690a	52	struct clock_event_device evt = (struct clock_event_device **)dev_id;
a850c3f6 SB	53	/* Stop the timer tick */
a850c3f6 SB	54	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
2a00c106	55	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	56	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	57	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	58	}
3e4ea372 AH	59	evt->event_handler(evt);
	60	return IRQ_HANDLED;
	61	}
	62
3e4ea372 AH	63	static int msm_timer_set_next_event(unsigned long cycles,
	64	struct clock_event_device *evt)
	65	{
2a00c106	66	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	67
4080d2d1 SB	68	ctrl &= ~TIMER_ENABLE_EN;
	69	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	70
	71	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
2a00c106	72	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
e25e3d1f SB	73
	74	if (sts_base)
	75	while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
	76	cpu_relax();
	77
2a00c106	78	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	79	return 0;
	80	}
	81
	82	static void msm_timer_set_mode(enum clock_event_mode mode,
	83	struct clock_event_device *evt)
	84	{
a850c3f6 SB	85	u32 ctrl;
a850c3f6 SB	86
2a00c106	87	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	88	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	89
3e4ea372 AH	90	switch (mode) {
	91	case CLOCK_EVT_MODE_RESUME:
	92	case CLOCK_EVT_MODE_PERIODIC:
	93	break;
	94	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	95	/* Timer is enabled in set_next_event */
3e4ea372 AH	96	break;
	97	case CLOCK_EVT_MODE_UNUSED:
	98	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	99	break;
3e4ea372 AH	100	}
2a00c106	101	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
3e4ea372 AH	102	}
3e4ea372 AH	103
2a00c106 SB	104	static struct clock_event_device msm_clockevent = {
	105	.name = "gp_timer",
	106	.features = CLOCK_EVT_FEAT_ONESHOT,
2a00c106 SB	107	.rating = 200,
	108	.set_next_event = msm_timer_set_next_event,
	109	.set_mode = msm_timer_set_mode,
	110	};
	111
	112	static union {
	113	struct clock_event_device *evt;
3b5909de	114	struct clock_event_device * __percpu *percpu_evt;
2a00c106 SB	115	} msm_evt;
	116
	117	static void __iomem *source_base;
	118
f8e56c42	119	static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	120	{
	121	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	122	}
	123
f8e56c42	124	static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
2a00c106 SB	125	{
	126	/*
	127	* Shift timer count down by a constant due to unreliable lower bits
	128	* on some targets.
	129	*/
2081a6b5	130	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
2a00c106 SB	131	}
	132
	133	static struct clocksource msm_clocksource = {
	134	.name = "dg_timer",
	135	.rating = 300,
	136	.read = msm_read_timer_count,
2081a6b5	137	.mask = CLOCKSOURCE_MASK(32),
2a00c106	138	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	139	};
3e4ea372 AH	140
5ca709c1	141	#ifdef CONFIG_LOCAL_TIMERS
8bd26e3a	142	static int msm_local_timer_setup(struct clock_event_device *evt)
5ca709c1 MZ	143	{
	144	/* Use existing clock_event for cpu 0 */
	145	if (!smp_processor_id())
	146	return 0;
	147
5ca709c1 MZ	148	evt->irq = msm_clockevent.irq;
	149	evt->name = "local_timer";
	150	evt->features = msm_clockevent.features;
	151	evt->rating = msm_clockevent.rating;
	152	evt->set_mode = msm_timer_set_mode;
	153	evt->set_next_event = msm_timer_set_next_event;
5ca709c1 MZ	154
5ca709c1 MZ	155	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
838a2ae8	156	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
66a89509	157	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	158	return 0;
	159	}
	160
	161	static void msm_local_timer_stop(struct clock_event_device *evt)
	162	{
	163	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	164	disable_percpu_irq(evt->irq);
	165	}
	166
8bd26e3a	167	static struct local_timer_ops msm_local_timer_ops = {
5ca709c1 MZ	168	.setup = msm_local_timer_setup,
	169	.stop = msm_local_timer_stop,
	170	};
	171	#endif /* CONFIG_LOCAL_TIMERS */
	172
f8e56c42 SB	173	static notrace u32 msm_sched_clock_read(void)
	174	{
	175	return msm_clocksource.read(&msm_clocksource);
	176	}
	177
4312a7ef SB	178	static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef SB	179	bool percpu)
3e4ea372	180	{
2a00c106 SB	181	struct clock_event_device *ce = &msm_clockevent;
2a00c106 SB	182	struct clocksource *cs = &msm_clocksource;
3e4ea372 AH	183	int res;
3e4ea372 AH	184
dd15ab81	185	ce->cpumask = cpumask_of(0);
4312a7ef	186	ce->irq = irq;
dd15ab81	187
27fdb577	188	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
4312a7ef	189	if (percpu) {
2a00c106 SB	190	msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
2a00c106 SB	191	if (!msm_evt.percpu_evt) {
dd15ab81 SB	192	pr_err("memory allocation failed for %s\n", ce->name);
dd15ab81 SB	193	goto err;
28af690a	194	}
2a00c106	195	*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
dd15ab81	196	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
2a00c106	197	ce->name, msm_evt.percpu_evt);
5ca709c1	198	if (!res) {
66a89509	199	enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	200	#ifdef CONFIG_LOCAL_TIMERS
	201	local_timer_register(&msm_local_timer_ops);
	202	#endif
	203	}
dd15ab81	204	} else {
2a00c106	205	msm_evt.evt = ce;
dd15ab81 SB	206	res = request_irq(ce->irq, msm_timer_interrupt,
dd15ab81 SB	207	IRQF_TIMER \| IRQF_NOBALANCING \|
2a00c106	208	IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
3e4ea372	209	}
dd15ab81 SB	210
	211	if (res)
	212	pr_err("request_irq failed for %s\n", ce->name);
dd15ab81	213	err:
2a00c106	214	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	215	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	216	if (res)
2a00c106	217	pr_err("clocksource_register failed\n");
4312a7ef	218	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
3e4ea372 AH	219	}
3e4ea372 AH	220
6e332163	221	#ifdef CONFIG_OF
eebdb0c1 SB	222	static const struct of_device_id msm_timer_match[] __initconst = {
	223	{ .compatible = "qcom,kpss-timer" },
	224	{ .compatible = "qcom,scss-timer" },
6e332163 SB	225	{ },
	226	};
	227
6bb27d73	228	void __init msm_dt_timer_init(void)
6e332163 SB	229	{
	230	struct device_node *np;
	231	u32 freq;
	232	int irq;
	233	struct resource res;
	234	u32 percpu_offset;
eebdb0c1 SB	235	void __iomem *base;
eebdb0c1 SB	236	void __iomem *cpu0_base;
6e332163	237
eebdb0c1	238	np = of_find_matching_node(NULL, msm_timer_match);
6e332163	239	if (!np) {
eebdb0c1	240	pr_err("Can't find msm timer DT node\n");
6e332163 SB	241	return;
	242	}
	243
eebdb0c1 SB	244	base = of_iomap(np, 0);
eebdb0c1 SB	245	if (!base) {
6e332163 SB	246	pr_err("Failed to map event base\n");
	247	return;
	248	}
	249
eebdb0c1 SB	250	/* We use GPT0 for the clockevent */
eebdb0c1 SB	251	irq = irq_of_parse_and_map(np, 1);
6e332163 SB	252	if (irq <= 0) {
	253	pr_err("Can't get irq\n");
	254	return;
	255	}
6e332163	256
eebdb0c1	257	/* We use CPU0's DGT for the clocksource */
6e332163 SB	258	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	259	percpu_offset = 0;
	260
	261	if (of_address_to_resource(np, 0, &res)) {
	262	pr_err("Failed to parse DGT resource\n");
	263	return;
	264	}
	265
eebdb0c1 SB	266	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
eebdb0c1 SB	267	if (!cpu0_base) {
6e332163 SB	268	pr_err("Failed to map source base\n");
	269	return;
	270	}
	271
6e332163 SB	272	if (of_property_read_u32(np, "clock-frequency", &freq)) {
	273	pr_err("Unknown frequency\n");
	274	return;
	275	}
	276	of_node_put(np);
	277
eebdb0c1	278	event_base = base + 0x4;
e25e3d1f	279	sts_base = base + 0x88;
eebdb0c1 SB	280	source_base = cpu0_base + 0x24;
	281	freq /= 4;
	282	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
	283
6e332163 SB	284	msm_timer_init(freq, 32, irq, !!percpu_offset);
6e332163 SB	285	}
6e332163 SB	286	#endif
6e332163 SB	287
e25e3d1f SB	288	static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
e25e3d1f SB	289	u32 sts)
4312a7ef	290	{
eebdb0c1 SB	291	void __iomem *base;
	292
	293	base = ioremap(addr, SZ_256);
	294	if (!base) {
	295	pr_err("Failed to map timer base\n");
	296	return -ENOMEM;
4312a7ef	297	}
eebdb0c1 SB	298	event_base = base + event;
eebdb0c1 SB	299	source_base = base + source;
e25e3d1f SB	300	if (sts)
e25e3d1f SB	301	sts_base = base + sts;
eebdb0c1	302
4312a7ef SB	303	return 0;
	304	}
	305
6bb27d73	306	void __init msm7x01_timer_init(void)
4312a7ef SB	307	{
	308	struct clocksource *cs = &msm_clocksource;
	309
e25e3d1f	310	if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
4312a7ef SB	311	return;
	312	cs->read = msm_read_timer_count_shift;
	313	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	314	/* 600 KHz */
	315	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
	316	false);
	317	}
	318
6bb27d73	319	void __init msm7x30_timer_init(void)
4312a7ef	320	{
e25e3d1f	321	if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
4312a7ef SB	322	return;
	323	msm_timer_init(24576000 / 4, 32, 1, false);
	324	}
	325
6bb27d73	326	void __init qsd8x50_timer_init(void)
4312a7ef	327	{
e25e3d1f	328	if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
4312a7ef SB	329	return;
	330	msm_timer_init(19200000 / 4, 32, 7, false);
	331	}