[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>

#include "common.h"

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
#define TIMER_ENABLE_EN                 BIT(0)
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL             0x0030
#define DGT_CLK_CTL_DIV_4	0x3

#define GPT_HZ 32768

#define MSM_DGT_SHIFT 5

static void __iomem *event_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}

static struct clock_event_device msm_clockevent = {
	.name		= "gp_timer",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= msm_timer_set_next_event,
	.set_mode	= msm_timer_set_mode,
};

static union {
	struct clock_event_device *evt;
	struct clock_event_device __percpu **percpu_evt;
} msm_evt;

static void __iomem *source_base;

static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

#ifdef CONFIG_LOCAL_TIMERS
static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
{
	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	evt->irq = msm_clockevent.irq;
	evt->name = "local_timer";
	evt->features = msm_clockevent.features;
	evt->rating = msm_clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;
	evt->shift = msm_clockevent.shift;
	evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
	evt->min_delta_ns = clockevent_delta2ns(4, evt);

	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
	clockevents_register_device(evt);
	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void msm_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}

static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
	.setup	= msm_local_timer_setup,
	.stop	= msm_local_timer_stop,
};
#endif /* CONFIG_LOCAL_TIMERS */

static notrace u32 msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clock_event_device *ce = &msm_clockevent;
	struct clocksource *cs = &msm_clocksource;
	int res;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	ce->cpumask = cpumask_of(0);
	ce->irq = irq;

	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
	if (percpu) {
		msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
		if (!msm_evt.percpu_evt) {
			pr_err("memory allocation failed for %s\n", ce->name);
			goto err;
		}
		*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
					 ce->name, msm_evt.percpu_evt);
		if (!res) {
			enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_LOCAL_TIMERS
			local_timer_register(&msm_local_timer_ops);
#endif
		}
	} else {
		msm_evt.evt = ce;
		res = request_irq(ce->irq, msm_timer_interrupt,
				  IRQF_TIMER | IRQF_NOBALANCING |
				  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
	}

	if (res)
		pr_err("request_irq failed for %s\n", ce->name);
err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
}

#ifdef CONFIG_OF
static const struct of_device_id msm_dgt_match[] __initconst = {
	{ .compatible = "qcom,msm-dgt" },
	{ },
};

static const struct of_device_id msm_gpt_match[] __initconst = {
	{ .compatible = "qcom,msm-gpt" },
	{ },
};

static void __init msm_dt_timer_init(void)
{
	struct device_node *np;
	u32 freq;
	int irq;
	struct resource res;
	u32 percpu_offset;
	void __iomem *dgt_clk_ctl;

	np = of_find_matching_node(NULL, msm_gpt_match);
	if (!np) {
		pr_err("Can't find GPT DT node\n");
		return;
	}

	event_base = of_iomap(np, 0);
	if (!event_base) {
		pr_err("Failed to map event base\n");
		return;
	}

	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return;
	}
	of_node_put(np);

	np = of_find_matching_node(NULL, msm_dgt_match);
	if (!np) {
		pr_err("Can't find DGT DT node\n");
		return;
	}

	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("Failed to parse DGT resource\n");
		return;
	}

	source_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!source_base) {
		pr_err("Failed to map source base\n");
		return;
	}

	if (!of_address_to_resource(np, 1, &res)) {
		dgt_clk_ctl = ioremap(res.start + percpu_offset,
				      resource_size(&res));
		if (!dgt_clk_ctl) {
			pr_err("Failed to map DGT control base\n");
			return;
		}
		writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
		iounmap(dgt_clk_ctl);
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return;
	}
	of_node_put(np);

	msm_timer_init(freq, 32, irq, !!percpu_offset);
}

struct sys_timer msm_dt_timer = {
	.init = msm_dt_timer_init
};
#endif

static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
{
	event_base = ioremap(event, SZ_64);
	if (!event_base) {
		pr_err("Failed to map event base\n");
		return 1;
	}
	source_base = ioremap(source, SZ_64);
	if (!source_base) {
		pr_err("Failed to map source base\n");
		return 1;
	}
	return 0;
}

static void __init msm7x01_timer_init(void)
{
	struct clocksource *cs = &msm_clocksource;

	if (msm_timer_map(0xc0100000, 0xc0100010))
		return;
	cs->read = msm_read_timer_count_shift;
	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	/* 600 KHz */
	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
			false);
}

struct sys_timer msm7x01_timer = {
	.init = msm7x01_timer_init
};

static void __init msm7x30_timer_init(void)
{
	if (msm_timer_map(0xc0100004, 0xc0100024))
		return;
	msm_timer_init(24576000 / 4, 32, 1, false);
}

struct sys_timer msm7x30_timer = {
	.init = msm7x30_timer_init
};

static void __init msm8x60_timer_init(void)
{
	if (msm_timer_map(0x02000004, 0x02040024))
		return;
	writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
	msm_timer_init(27000000 / 4, 32, 17, true);
}

struct sys_timer msm8x60_timer = {
	.init = msm8x60_timer_init
};

static void __init msm8960_timer_init(void)
{
	if (msm_timer_map(0x0200A004, 0x0208A024))
		return;
	writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
	msm_timer_init(27000000 / 4, 32, 17, true);
}

struct sys_timer msm8960_timer = {
	.init = msm8960_timer_init
};

static void __init qsd8x50_timer_init(void)
{
	if (msm_timer_map(0xAC100000, 0xAC100010))
		return;
	msm_timer_init(19200000 / 4, 32, 7, false);
}

struct sys_timer qsd8x50_timer = {
	.init = qsd8x50_timer_init
};
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
4312a7ef	4	* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
3e4ea372	19	#include <linux/init.h>
3e4ea372 AH	20	#include <linux/interrupt.h>
3e4ea372 AH	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
6e332163 SB	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
3e4ea372 AH	26
3e4ea372 AH	27	#include <asm/mach/time.h>
ebf30dc9	28	#include <asm/hardware/gic.h>
4a184075	29	#include <asm/localtimer.h>
f8e56c42	30	#include <asm/sched_clock.h>
ebf30dc9	31
4312a7ef	32	#include "common.h"
3e4ea372 AH	33
	34	#define TIMER_MATCH_VAL 0x0000
	35	#define TIMER_COUNT_VAL 0x0004
	36	#define TIMER_ENABLE 0x0008
4a184075 SB	37	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
4a184075 SB	38	#define TIMER_ENABLE_EN BIT(0)
3e4ea372	39	#define TIMER_CLEAR 0x000C
4312a7ef	40	#define DGT_CLK_CTL 0x0030
4a184075	41	#define DGT_CLK_CTL_DIV_4 0x3
3e4ea372 AH	42
3e4ea372 AH	43	#define GPT_HZ 32768
672039f0	44
2081a6b5	45	#define MSM_DGT_SHIFT 5
3e4ea372	46
2a00c106	47	static void __iomem *event_base;
a850c3f6	48
3e4ea372 AH	49	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	50	{
28af690a	51	struct clock_event_device evt = (struct clock_event_device **)dev_id;
a850c3f6 SB	52	/* Stop the timer tick */
a850c3f6 SB	53	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
2a00c106	54	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	55	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	56	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	57	}
3e4ea372 AH	58	evt->event_handler(evt);
	59	return IRQ_HANDLED;
	60	}
	61
3e4ea372 AH	62	static int msm_timer_set_next_event(unsigned long cycles,
	63	struct clock_event_device *evt)
	64	{
2a00c106	65	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	66
2a00c106 SB	67	writel_relaxed(0, event_base + TIMER_CLEAR);
	68	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	69	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	70	return 0;
	71	}
	72
	73	static void msm_timer_set_mode(enum clock_event_mode mode,
	74	struct clock_event_device *evt)
	75	{
a850c3f6 SB	76	u32 ctrl;
a850c3f6 SB	77
2a00c106	78	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	79	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	80
3e4ea372 AH	81	switch (mode) {
	82	case CLOCK_EVT_MODE_RESUME:
	83	case CLOCK_EVT_MODE_PERIODIC:
	84	break;
	85	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	86	/* Timer is enabled in set_next_event */
3e4ea372 AH	87	break;
	88	case CLOCK_EVT_MODE_UNUSED:
	89	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	90	break;
3e4ea372 AH	91	}
2a00c106	92	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
3e4ea372 AH	93	}
3e4ea372 AH	94
2a00c106 SB	95	static struct clock_event_device msm_clockevent = {
	96	.name = "gp_timer",
	97	.features = CLOCK_EVT_FEAT_ONESHOT,
2a00c106 SB	98	.rating = 200,
	99	.set_next_event = msm_timer_set_next_event,
	100	.set_mode = msm_timer_set_mode,
	101	};
	102
	103	static union {
	104	struct clock_event_device *evt;
	105	struct clock_event_device __percpu **percpu_evt;
	106	} msm_evt;
	107
	108	static void __iomem *source_base;
	109
f8e56c42	110	static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	111	{
	112	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	113	}
	114
f8e56c42	115	static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
2a00c106 SB	116	{
	117	/*
	118	* Shift timer count down by a constant due to unreliable lower bits
	119	* on some targets.
	120	*/
2081a6b5	121	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
2a00c106 SB	122	}
	123
	124	static struct clocksource msm_clocksource = {
	125	.name = "dg_timer",
	126	.rating = 300,
	127	.read = msm_read_timer_count,
2081a6b5	128	.mask = CLOCKSOURCE_MASK(32),
2a00c106	129	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	130	};
3e4ea372 AH	131
5ca709c1 MZ	132	#ifdef CONFIG_LOCAL_TIMERS
	133	static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
	134	{
	135	/* Use existing clock_event for cpu 0 */
	136	if (!smp_processor_id())
	137	return 0;
	138
	139	writel_relaxed(0, event_base + TIMER_ENABLE);
	140	writel_relaxed(0, event_base + TIMER_CLEAR);
	141	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	142	evt->irq = msm_clockevent.irq;
	143	evt->name = "local_timer";
	144	evt->features = msm_clockevent.features;
	145	evt->rating = msm_clockevent.rating;
	146	evt->set_mode = msm_timer_set_mode;
	147	evt->set_next_event = msm_timer_set_next_event;
	148	evt->shift = msm_clockevent.shift;
	149	evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
	150	evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
	151	evt->min_delta_ns = clockevent_delta2ns(4, evt);
	152
	153	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
	154	clockevents_register_device(evt);
66a89509	155	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	156	return 0;
	157	}
	158
	159	static void msm_local_timer_stop(struct clock_event_device *evt)
	160	{
	161	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	162	disable_percpu_irq(evt->irq);
	163	}
	164
	165	static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
	166	.setup = msm_local_timer_setup,
	167	.stop = msm_local_timer_stop,
	168	};
	169	#endif /* CONFIG_LOCAL_TIMERS */
	170
f8e56c42 SB	171	static notrace u32 msm_sched_clock_read(void)
	172	{
	173	return msm_clocksource.read(&msm_clocksource);
	174	}
	175
4312a7ef SB	176	static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef SB	177	bool percpu)
3e4ea372	178	{
2a00c106 SB	179	struct clock_event_device *ce = &msm_clockevent;
2a00c106 SB	180	struct clocksource *cs = &msm_clocksource;
3e4ea372 AH	181	int res;
3e4ea372 AH	182
2a00c106 SB	183	writel_relaxed(0, event_base + TIMER_ENABLE);
	184	writel_relaxed(0, event_base + TIMER_CLEAR);
	185	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
dd15ab81	186	ce->cpumask = cpumask_of(0);
4312a7ef	187	ce->irq = irq;
dd15ab81	188
27fdb577	189	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
4312a7ef	190	if (percpu) {
2a00c106 SB	191	msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
2a00c106 SB	192	if (!msm_evt.percpu_evt) {
dd15ab81 SB	193	pr_err("memory allocation failed for %s\n", ce->name);
dd15ab81 SB	194	goto err;
28af690a	195	}
2a00c106	196	*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
dd15ab81	197	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
2a00c106	198	ce->name, msm_evt.percpu_evt);
5ca709c1	199	if (!res) {
66a89509	200	enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	201	#ifdef CONFIG_LOCAL_TIMERS
	202	local_timer_register(&msm_local_timer_ops);
	203	#endif
	204	}
dd15ab81	205	} else {
2a00c106	206	msm_evt.evt = ce;
dd15ab81 SB	207	res = request_irq(ce->irq, msm_timer_interrupt,
dd15ab81 SB	208	IRQF_TIMER \| IRQF_NOBALANCING \|
2a00c106	209	IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
3e4ea372	210	}
dd15ab81 SB	211
	212	if (res)
	213	pr_err("request_irq failed for %s\n", ce->name);
dd15ab81	214	err:
2a00c106	215	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	216	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	217	if (res)
2a00c106	218	pr_err("clocksource_register failed\n");
4312a7ef	219	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
3e4ea372 AH	220	}
3e4ea372 AH	221
6e332163 SB	222	#ifdef CONFIG_OF
	223	static const struct of_device_id msm_dgt_match[] __initconst = {
	224	{ .compatible = "qcom,msm-dgt" },
	225	{ },
	226	};
	227
	228	static const struct of_device_id msm_gpt_match[] __initconst = {
	229	{ .compatible = "qcom,msm-gpt" },
	230	{ },
	231	};
	232
	233	static void __init msm_dt_timer_init(void)
	234	{
	235	struct device_node *np;
	236	u32 freq;
	237	int irq;
	238	struct resource res;
	239	u32 percpu_offset;
	240	void __iomem *dgt_clk_ctl;
	241
	242	np = of_find_matching_node(NULL, msm_gpt_match);
	243	if (!np) {
	244	pr_err("Can't find GPT DT node\n");
	245	return;
	246	}
	247
	248	event_base = of_iomap(np, 0);
	249	if (!event_base) {
	250	pr_err("Failed to map event base\n");
	251	return;
	252	}
	253
	254	irq = irq_of_parse_and_map(np, 0);
	255	if (irq <= 0) {
	256	pr_err("Can't get irq\n");
	257	return;
	258	}
	259	of_node_put(np);
	260
	261	np = of_find_matching_node(NULL, msm_dgt_match);
	262	if (!np) {
	263	pr_err("Can't find DGT DT node\n");
	264	return;
	265	}
	266
	267	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	268	percpu_offset = 0;
	269
	270	if (of_address_to_resource(np, 0, &res)) {
	271	pr_err("Failed to parse DGT resource\n");
	272	return;
	273	}
	274
	275	source_base = ioremap(res.start + percpu_offset, resource_size(&res));
	276	if (!source_base) {
	277	pr_err("Failed to map source base\n");
	278	return;
	279	}
	280
	281	if (!of_address_to_resource(np, 1, &res)) {
	282	dgt_clk_ctl = ioremap(res.start + percpu_offset,
	283	resource_size(&res));
	284	if (!dgt_clk_ctl) {
	285	pr_err("Failed to map DGT control base\n");
286	return;
287	}
288	writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
289	iounmap(dgt_clk_ctl);
290	}
291
292	if (of_property_read_u32(np, "clock-frequency", &freq)) {
293	pr_err("Unknown frequency\n");
294	return;
295	}
296	of_node_put(np);
297
298	msm_timer_init(freq, 32, irq, !!percpu_offset);
299	}
300
301	struct sys_timer msm_dt_timer = {
302	.init = msm_dt_timer_init
303	};
304	#endif
305
4312a7ef SB	306	static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
	307	{
	308	event_base = ioremap(event, SZ_64);
	309	if (!event_base) {
	310	pr_err("Failed to map event base\n");
	311	return 1;
	312	}
	313	source_base = ioremap(source, SZ_64);
	314	if (!source_base) {
	315	pr_err("Failed to map source base\n");
	316	return 1;
	317	}
	318	return 0;
	319	}
	320
	321	static void __init msm7x01_timer_init(void)
	322	{
	323	struct clocksource *cs = &msm_clocksource;
	324
	325	if (msm_timer_map(0xc0100000, 0xc0100010))
	326	return;
	327	cs->read = msm_read_timer_count_shift;
	328	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	329	/* 600 KHz */
	330	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
	331	false);
	332	}
	333
	334	struct sys_timer msm7x01_timer = {
	335	.init = msm7x01_timer_init
	336	};
	337
	338	static void __init msm7x30_timer_init(void)
	339	{
	340	if (msm_timer_map(0xc0100004, 0xc0100024))
	341	return;
	342	msm_timer_init(24576000 / 4, 32, 1, false);
	343	}
	344
	345	struct sys_timer msm7x30_timer = {
	346	.init = msm7x30_timer_init
	347	};
	348
	349	static void __init msm8x60_timer_init(void)
	350	{
	351	if (msm_timer_map(0x02000004, 0x02040024))
	352	return;
	353	writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
	354	msm_timer_init(27000000 / 4, 32, 17, true);
	355	}
	356
	357	struct sys_timer msm8x60_timer = {
	358	.init = msm8x60_timer_init
	359	};
	360
	361	static void __init msm8960_timer_init(void)
	362	{
	363	if (msm_timer_map(0x0200A004, 0x0208A024))
	364	return;
	365	writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
	366	msm_timer_init(27000000 / 4, 32, 17, true);
	367	}
	368
	369	struct sys_timer msm8960_timer = {
370	.init = msm8960_timer_init
371	};
372
373	static void __init qsd8x50_timer_init(void)
374	{
375	if (msm_timer_map(0xAC100000, 0xAC100010))
376	return;
377	msm_timer_init(19200000 / 4, 32, 7, false);
378	}
379
380	struct sys_timer qsd8x50_timer = {
381	.init = qsd8x50_timer_init
3e4ea372	382	};