[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/* linux/arch/arm/mach-msm/timer.c
 *
 * Copyright (C) 2007 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <mach/msm_iomap.h>

#ifndef MSM_DGT_BASE
#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
#endif

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    2
#define TIMER_ENABLE_EN                 1
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL             0x0034
enum {
	DGT_CLK_CTL_DIV_1 = 0,
	DGT_CLK_CTL_DIV_2 = 1,
	DGT_CLK_CTL_DIV_3 = 2,
	DGT_CLK_CTL_DIV_4 = 3,
};
#define CSR_PROTECTION          0x0020
#define CSR_PROTECTION_EN               1

#define GPT_HZ 32768

#if defined(CONFIG_ARCH_QSD8X50)
#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#else
#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
#define MSM_DGT_SHIFT (5)
#endif

struct msm_clock {
	struct clock_event_device   clockevent;
	struct clocksource          clocksource;
	struct irqaction            irq;
	void __iomem                *regbase;
	uint32_t                    freq;
	uint32_t                    shift;
};

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static cycle_t msm_gpt_read(struct clocksource *cs)
{
	return readl(MSM_GPT_BASE + TIMER_COUNT_VAL);
}

static cycle_t msm_dgt_read(struct clocksource *cs)
{
	return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
	uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL);
	uint32_t alarm = now + (cycles << clock->shift);
	int late;

	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
	now = readl(clock->regbase + TIMER_COUNT_VAL);
	late = now - alarm;
	if (late >= (-2 << clock->shift) && late < DGT_HZ*5) {
		printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, "
		       "alarm already expired, now %x, alarm %x, late %d\n",
		       cycles, clock->clockevent.name, now, alarm, late);
		return -ETIME;
	}
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		writel(0, clock->regbase + TIMER_ENABLE);
		break;
	}
}

static struct msm_clock msm_clocks[] = {
	{
		.clockevent = {
			.name           = "gp_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32,
			.rating         = 200,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.clocksource = {
			.name           = "gp_timer",
			.rating         = 200,
			.read           = msm_gpt_read,
			.mask           = CLOCKSOURCE_MASK(32),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.irq = {
			.name    = "gp_timer",
			.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
			.handler = msm_timer_interrupt,
			.dev_id  = &msm_clocks[0].clockevent,
			.irq     = INT_GP_TIMER_EXP
		},
		.regbase = MSM_GPT_BASE,
		.freq = GPT_HZ
	},
	{
		.clockevent = {
			.name           = "dg_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32 + MSM_DGT_SHIFT,
			.rating         = 300,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.clocksource = {
			.name           = "dg_timer",
			.rating         = 300,
			.read           = msm_dgt_read,
			.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.irq = {
			.name    = "dg_timer",
			.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
			.handler = msm_timer_interrupt,
			.dev_id  = &msm_clocks[1].clockevent,
			.irq     = INT_DEBUG_TIMER_EXP
		},
		.regbase = MSM_DGT_BASE,
		.freq = DGT_HZ >> MSM_DGT_SHIFT,
		.shift = MSM_DGT_SHIFT
	}
};

static void __init msm_timer_init(void)
{
	int i;
	int res;

#ifdef CONFIG_ARCH_MSM8X60
	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
#endif

	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
		struct msm_clock *clock = &msm_clocks[i];
		struct clock_event_device *ce = &clock->clockevent;
		struct clocksource *cs = &clock->clocksource;
		writel(0, clock->regbase + TIMER_ENABLE);
		writel(0, clock->regbase + TIMER_CLEAR);
		writel(~0, clock->regbase + TIMER_MATCH_VAL);

		ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
		/* allow at least 10 seconds to notice that the timer wrapped */
		ce->max_delta_ns =
			clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
		/* 4 gets rounded down to 3 */
		ce->min_delta_ns = clockevent_delta2ns(4, ce);
		ce->cpumask = cpumask_of(0);

		res = clocksource_register_hz(cs, clock->freq);
		if (res)
			printk(KERN_ERR "msm_timer_init: clocksource_register "
			       "failed for %s\n", cs->name);

		res = setup_irq(clock->irq.irq, &clock->irq);
		if (res)
			printk(KERN_ERR "msm_timer_init: setup_irq "
			       "failed for %s\n", cs->name);

		clockevents_register_device(ce);
	}
}

struct sys_timer msm_timer = {
	.init = msm_timer_init
};
Commit	Line	Data
3e4ea372 AH	1	/* linux/arch/arm/mach-msm/timer.c
	2	*
	3	* Copyright (C) 2007 Google, Inc.
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/time.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/irq.h>
	20	#include <linux/clk.h>
	21	#include <linux/clockchips.h>
	22	#include <linux/delay.h>
fced80c7	23	#include <linux/io.h>
3e4ea372 AH	24
3e4ea372 AH	25	#include <asm/mach/time.h>
a09e64fb	26	#include <mach/msm_iomap.h>
3e4ea372	27
83a2c0e4	28	#ifndef MSM_DGT_BASE
3e4ea372	29	#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
83a2c0e4	30	#endif
3e4ea372 AH	31
	32	#define TIMER_MATCH_VAL 0x0000
	33	#define TIMER_COUNT_VAL 0x0004
	34	#define TIMER_ENABLE 0x0008
	35	#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
	36	#define TIMER_ENABLE_EN 1
	37	#define TIMER_CLEAR 0x000C
672039f0 JO	38	#define DGT_CLK_CTL 0x0034
	39	enum {
	40	DGT_CLK_CTL_DIV_1 = 0,
	41	DGT_CLK_CTL_DIV_2 = 1,
	42	DGT_CLK_CTL_DIV_3 = 2,
	43	DGT_CLK_CTL_DIV_4 = 3,
	44	};
3e4ea372 AH	45	#define CSR_PROTECTION 0x0020
	46	#define CSR_PROTECTION_EN 1
	47
	48	#define GPT_HZ 32768
672039f0 JO	49
	50	#if defined(CONFIG_ARCH_QSD8X50)
	51	#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
	52	#define MSM_DGT_SHIFT (0)
	53	#elif defined(CONFIG_ARCH_MSM7X30) \|\| defined(CONFIG_ARCH_MSM8X60)
	54	#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
	55	#define MSM_DGT_SHIFT (0)
	56	#else
3e4ea372	57	#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
672039f0 JO	58	#define MSM_DGT_SHIFT (5)
672039f0 JO	59	#endif
3e4ea372 AH	60
	61	struct msm_clock {
	62	struct clock_event_device clockevent;
	63	struct clocksource clocksource;
	64	struct irqaction irq;
bcc0f6af	65	void __iomem *regbase;
3e4ea372 AH	66	uint32_t freq;
	67	uint32_t shift;
	68	};
	69
	70	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
	71	{
	72	struct clock_event_device *evt = dev_id;
	73	evt->event_handler(evt);
	74	return IRQ_HANDLED;
	75	}
	76
8e19608e	77	static cycle_t msm_gpt_read(struct clocksource *cs)
3e4ea372 AH	78	{
	79	return readl(MSM_GPT_BASE + TIMER_COUNT_VAL);
	80	}
	81
8e19608e	82	static cycle_t msm_dgt_read(struct clocksource *cs)
3e4ea372 AH	83	{
	84	return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;
	85	}
	86
	87	static int msm_timer_set_next_event(unsigned long cycles,
	88	struct clock_event_device *evt)
	89	{
	90	struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
	91	uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL);
	92	uint32_t alarm = now + (cycles << clock->shift);
	93	int late;
	94
	95	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
	96	now = readl(clock->regbase + TIMER_COUNT_VAL);
	97	late = now - alarm;
	98	if (late >= (-2 << clock->shift) && late < DGT_HZ*5) {
	99	printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, "
	100	"alarm already expired, now %x, alarm %x, late %d\n",
	101	cycles, clock->clockevent.name, now, alarm, late);
	102	return -ETIME;
	103	}
	104	return 0;
	105	}
	106
	107	static void msm_timer_set_mode(enum clock_event_mode mode,
	108	struct clock_event_device *evt)
	109	{
	110	struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
	111	switch (mode) {
	112	case CLOCK_EVT_MODE_RESUME:
	113	case CLOCK_EVT_MODE_PERIODIC:
	114	break;
	115	case CLOCK_EVT_MODE_ONESHOT:
	116	writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
	117	break;
	118	case CLOCK_EVT_MODE_UNUSED:
	119	case CLOCK_EVT_MODE_SHUTDOWN:
	120	writel(0, clock->regbase + TIMER_ENABLE);
	121	break;
	122	}
	123	}
	124
	125	static struct msm_clock msm_clocks[] = {
	126	{
	127	.clockevent = {
	128	.name = "gp_timer",
	129	.features = CLOCK_EVT_FEAT_ONESHOT,
	130	.shift = 32,
	131	.rating = 200,
	132	.set_next_event = msm_timer_set_next_event,
	133	.set_mode = msm_timer_set_mode,
	134	},
	135	.clocksource = {
	136	.name = "gp_timer",
	137	.rating = 200,
	138	.read = msm_gpt_read,
	139	.mask = CLOCKSOURCE_MASK(32),
3e4ea372 AH	140	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	141	},
	142	.irq = {
	143	.name = "gp_timer",
	144	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_RISING,
	145	.handler = msm_timer_interrupt,
	146	.dev_id = &msm_clocks[0].clockevent,
	147	.irq = INT_GP_TIMER_EXP
	148	},
	149	.regbase = MSM_GPT_BASE,
	150	.freq = GPT_HZ
	151	},
	152	{
	153	.clockevent = {
	154	.name = "dg_timer",
	155	.features = CLOCK_EVT_FEAT_ONESHOT,
	156	.shift = 32 + MSM_DGT_SHIFT,
	157	.rating = 300,
	158	.set_next_event = msm_timer_set_next_event,
	159	.set_mode = msm_timer_set_mode,
	160	},
	161	.clocksource = {
	162	.name = "dg_timer",
	163	.rating = 300,
	164	.read = msm_dgt_read,
	165	.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
3e4ea372 AH	166	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	167	},
	168	.irq = {
	169	.name = "dg_timer",
	170	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_RISING,
	171	.handler = msm_timer_interrupt,
	172	.dev_id = &msm_clocks[1].clockevent,
	173	.irq = INT_DEBUG_TIMER_EXP
	174	},
	175	.regbase = MSM_DGT_BASE,
	176	.freq = DGT_HZ >> MSM_DGT_SHIFT,
	177	.shift = MSM_DGT_SHIFT
	178	}
	179	};
	180
	181	static void __init msm_timer_init(void)
	182	{
	183	int i;
	184	int res;
	185
672039f0 JO	186	#ifdef CONFIG_ARCH_MSM8X60
	187	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	188	#endif
	189
3e4ea372 AH	190	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
	191	struct msm_clock *clock = &msm_clocks[i];
	192	struct clock_event_device *ce = &clock->clockevent;
	193	struct clocksource *cs = &clock->clocksource;
	194	writel(0, clock->regbase + TIMER_ENABLE);
	195	writel(0, clock->regbase + TIMER_CLEAR);
	196	writel(~0, clock->regbase + TIMER_MATCH_VAL);
	197
	198	ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
	199	/* allow at least 10 seconds to notice that the timer wrapped */
	200	ce->max_delta_ns =
	201	clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
	202	/* 4 gets rounded down to 3 */
	203	ce->min_delta_ns = clockevent_delta2ns(4, ce);
320ab2b0	204	ce->cpumask = cpumask_of(0);
3e4ea372	205
ff9c9772	206	res = clocksource_register_hz(cs, clock->freq);
3e4ea372 AH	207	if (res)
	208	printk(KERN_ERR "msm_timer_init: clocksource_register "
	209	"failed for %s\n", cs->name);
	210
	211	res = setup_irq(clock->irq.irq, &clock->irq);
	212	if (res)
	213	printk(KERN_ERR "msm_timer_init: setup_irq "
	214	"failed for %s\n", cs->name);
	215
	216	clockevents_register_device(ce);
	217	}
	218	}
	219
	220	struct sys_timer msm_timer = {
	221	.init = msm_timer_init
	222	};