[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/localtimer.h>

#include <mach/msm_iomap.h>
#include <mach/cpu.h>
#include <mach/board.h>

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
#define TIMER_ENABLE_EN                 BIT(0)
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL             0x0034
#define DGT_CLK_CTL_DIV_4	0x3

#define GPT_HZ 32768

#define MSM_GLOBAL_TIMER MSM_CLOCK_GPT

/* TODO: Remove these ifdefs */
#if defined(CONFIG_ARCH_QSD8X50)
#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM7X30)
#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#else
#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
#define MSM_DGT_SHIFT (5)
#endif

struct msm_clock {
	struct clock_event_device   clockevent;
	struct clocksource          clocksource;
	unsigned int		    irq;
	void __iomem                *regbase;
	uint32_t                    freq;
	uint32_t                    shift;
	void __iomem                *global_counter;
	void __iomem                *local_counter;
	union {
		struct clock_event_device		*evt;
		struct clock_event_device __percpu	**percpu_evt;
	};		
};

enum {
	MSM_CLOCK_GPT,
	MSM_CLOCK_DGT,
	NR_TIMERS,
};


static struct msm_clock msm_clocks[];

static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt);

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	if (evt->event_handler == NULL)
		return IRQ_HANDLED;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		struct msm_clock *clock = clockevent_to_clock(evt);
		u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static cycle_t msm_read_timer_count(struct clocksource *cs)
{
	struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);

	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return readl(clk->global_counter) >> clk->shift;
}

static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
{
#ifdef CONFIG_SMP
	int i;
	for (i = 0; i < NR_TIMERS; i++)
		if (evt == &(msm_clocks[i].clockevent))
			return &msm_clocks[i];
	return &msm_clocks[MSM_GLOBAL_TIMER];
#else
	return container_of(evt, struct msm_clock, clockevent);
#endif
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	struct msm_clock *clock = clockevent_to_clock(evt);
	u32 match = cycles << clock->shift;
	u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);

	writel_relaxed(0, clock->regbase + TIMER_CLEAR);
	writel_relaxed(match, clock->regbase + TIMER_MATCH_VAL);
	writel_relaxed(ctrl | TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	struct msm_clock *clock = clockevent_to_clock(evt);
	u32 ctrl;

	ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);
}

static struct msm_clock msm_clocks[] = {
	[MSM_CLOCK_GPT] = {
		.clockevent = {
			.name           = "gp_timer",
			.features       = CLOCK_EVT_FEAT_ONESHOT,
			.shift          = 32,
			.rating         = 200,
			.set_next_event = msm_timer_set_next_event,
			.set_mode       = msm_timer_set_mode,
		},
		.irq = INT_GP_TIMER_EXP,
		.freq = GPT_HZ,
	},
	[MSM_CLOCK_DGT] = {
		.clocksource = {
			.name           = "dg_timer",
			.rating         = 300,
			.read           = msm_read_timer_count,
			.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
		},
		.freq = DGT_HZ >> MSM_DGT_SHIFT,
		.shift = MSM_DGT_SHIFT,
	}
};

static void __init msm_timer_init(void)
{
	struct msm_clock *clock;
	struct clock_event_device *ce = &msm_clocks[MSM_CLOCK_GPT].clockevent;
	struct clocksource *cs = &msm_clocks[MSM_CLOCK_DGT].clocksource;
	int res;
	int global_offset = 0;


	if (cpu_is_msm7x01()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	} else if (cpu_is_msm7x30()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
	} else if (cpu_is_qsd8x50()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
		msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
		msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;

		/* Use CPU0's timer as the global timer. */
		global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
	} else
		BUG();

#ifdef CONFIG_ARCH_MSM_SCORPIONMP
	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
#endif

	clock = &msm_clocks[MSM_CLOCK_GPT];
	clock->local_counter = clock->regbase + TIMER_COUNT_VAL;

	writel_relaxed(0, clock->regbase + TIMER_ENABLE);
	writel_relaxed(0, clock->regbase + TIMER_CLEAR);
	writel_relaxed(~0, clock->regbase + TIMER_MATCH_VAL);
	ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
	/*
	 * allow at least 10 seconds to notice that the timer
	 * wrapped
	 */
	ce->max_delta_ns =
		clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
	/* 4 gets rounded down to 3 */
	ce->min_delta_ns = clockevent_delta2ns(4, ce);
	ce->cpumask = cpumask_of(0);

	ce->irq = clock->irq;
	if (cpu_is_msm8x60() || cpu_is_msm8960()) {
		clock->percpu_evt = alloc_percpu(struct clock_event_device *);
		if (!clock->percpu_evt) {
			pr_err("memory allocation failed for %s\n", ce->name);
			goto err;
		}

		*__this_cpu_ptr(clock->percpu_evt) = ce;
		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
					 ce->name, clock->percpu_evt);
		if (!res)
			enable_percpu_irq(ce->irq, 0);
	} else {
		clock->evt = ce;
		res = request_irq(ce->irq, msm_timer_interrupt,
				  IRQF_TIMER | IRQF_NOBALANCING |
				  IRQF_TRIGGER_RISING, ce->name, &clock->evt);
	}

	if (res)
		pr_err("request_irq failed for %s\n", ce->name);

	clockevents_register_device(ce);
err:
	clock = &msm_clocks[MSM_CLOCK_DGT];
	clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
	clock->global_counter = clock->local_counter + global_offset;
	writel_relaxed(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
	res = clocksource_register_hz(cs, clock->freq);
	if (res)
		pr_err("clocksource_register failed for %s\n", cs->name);
}

#ifdef CONFIG_LOCAL_TIMERS
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
	static bool local_timer_inited;
	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];

	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	if (!local_timer_inited) {
		writel(0, clock->regbase  + TIMER_ENABLE);
		writel(0, clock->regbase + TIMER_CLEAR);
		writel(~0, clock->regbase + TIMER_MATCH_VAL);
		local_timer_inited = true;
	}
	evt->irq = clock->irq;
	evt->name = "local_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = clock->clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;
	evt->shift = clock->clockevent.shift;
	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns =
		clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
	evt->min_delta_ns = clockevent_delta2ns(4, evt);

	*__this_cpu_ptr(clock->percpu_evt) = evt;
	enable_percpu_irq(evt->irq, 0);

	clockevents_register_device(evt);
	return 0;
}

void local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}
#endif /* CONFIG_LOCAL_TIMERS */

struct sys_timer msm_timer = {
	.init = msm_timer_init
};
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
dd15ab81	4	* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
3e4ea372	19	#include <linux/init.h>
3e4ea372 AH	20	#include <linux/interrupt.h>
3e4ea372 AH	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
3e4ea372 AH	23
3e4ea372 AH	24	#include <asm/mach/time.h>
ebf30dc9	25	#include <asm/hardware/gic.h>
4a184075	26	#include <asm/localtimer.h>
ebf30dc9	27
a09e64fb	28	#include <mach/msm_iomap.h>
8c27e6f3	29	#include <mach/cpu.h>
4a184075	30	#include <mach/board.h>
3e4ea372 AH	31
	32	#define TIMER_MATCH_VAL 0x0000
	33	#define TIMER_COUNT_VAL 0x0004
	34	#define TIMER_ENABLE 0x0008
4a184075 SB	35	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
4a184075 SB	36	#define TIMER_ENABLE_EN BIT(0)
3e4ea372	37	#define TIMER_CLEAR 0x000C
672039f0	38	#define DGT_CLK_CTL 0x0034
4a184075	39	#define DGT_CLK_CTL_DIV_4 0x3
3e4ea372 AH	40
3e4ea372 AH	41	#define GPT_HZ 32768
672039f0	42
dd15ab81	43	#define MSM_GLOBAL_TIMER MSM_CLOCK_GPT
94790ec2	44
8c27e6f3	45	/* TODO: Remove these ifdefs */
672039f0 JO	46	#if defined(CONFIG_ARCH_QSD8X50)
	47	#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
	48	#define MSM_DGT_SHIFT (0)
fdb9c3cd	49	#elif defined(CONFIG_ARCH_MSM7X30)
672039f0 JO	50	#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
672039f0 JO	51	#define MSM_DGT_SHIFT (0)
fdb9c3cd SB	52	#elif defined(CONFIG_ARCH_MSM8X60) \|\| defined(CONFIG_ARCH_MSM8960)
	53	#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
	54	#define MSM_DGT_SHIFT (0)
672039f0	55	#else
3e4ea372	56	#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
672039f0 JO	57	#define MSM_DGT_SHIFT (5)
672039f0 JO	58	#endif
3e4ea372 AH	59
	60	struct msm_clock {
	61	struct clock_event_device clockevent;
	62	struct clocksource clocksource;
28af690a	63	unsigned int irq;
bcc0f6af	64	void __iomem *regbase;
3e4ea372 AH	65	uint32_t freq;
3e4ea372 AH	66	uint32_t shift;
94790ec2 JO	67	void __iomem *global_counter;
94790ec2 JO	68	void __iomem *local_counter;
28af690a MZ	69	union {
	70	struct clock_event_device *evt;
	71	struct clock_event_device __percpu **percpu_evt;
	72	};
94790ec2 JO	73	};
	74
	75	enum {
	76	MSM_CLOCK_GPT,
	77	MSM_CLOCK_DGT,
	78	NR_TIMERS,
3e4ea372 AH	79	};
3e4ea372 AH	80
94790ec2 JO	81
94790ec2 JO	82	static struct msm_clock msm_clocks[];
94790ec2	83
a850c3f6 SB	84	static struct msm_clock clockevent_to_clock(struct clock_event_device evt);
a850c3f6 SB	85
3e4ea372 AH	86	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	87	{
28af690a	88	struct clock_event_device evt = (struct clock_event_device **)dev_id;
94790ec2 JO	89	if (evt->event_handler == NULL)
94790ec2 JO	90	return IRQ_HANDLED;
a850c3f6 SB	91	/* Stop the timer tick */
	92	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
	93	struct msm_clock *clock = clockevent_to_clock(evt);
	94	u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
	95	ctrl &= ~TIMER_ENABLE_EN;
	96	writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);
	97	}
3e4ea372 AH	98	evt->event_handler(evt);
	99	return IRQ_HANDLED;
	100	}
	101
94790ec2	102	static cycle_t msm_read_timer_count(struct clocksource *cs)
3e4ea372	103	{
94790ec2 JO	104	struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
94790ec2 JO	105
650f1567 JO	106	/*
	107	* Shift timer count down by a constant due to unreliable lower bits
	108	* on some targets.
	109	*/
	110	return readl(clk->global_counter) >> clk->shift;
3e4ea372 AH	111	}
3e4ea372 AH	112
94790ec2	113	static struct msm_clock clockevent_to_clock(struct clock_event_device evt)
3e4ea372	114	{
94790ec2 JO	115	#ifdef CONFIG_SMP
	116	int i;
	117	for (i = 0; i < NR_TIMERS; i++)
	118	if (evt == &(msm_clocks[i].clockevent))
	119	return &msm_clocks[i];
	120	return &msm_clocks[MSM_GLOBAL_TIMER];
	121	#else
	122	return container_of(evt, struct msm_clock, clockevent);
	123	#endif
3e4ea372 AH	124	}
	125
	126	static int msm_timer_set_next_event(unsigned long cycles,
	127	struct clock_event_device *evt)
	128	{
94790ec2	129	struct msm_clock *clock = clockevent_to_clock(evt);
a850c3f6 SB	130	u32 match = cycles << clock->shift;
a850c3f6 SB	131	u32 ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
3e4ea372	132
a850c3f6 SB	133	writel_relaxed(0, clock->regbase + TIMER_CLEAR);
	134	writel_relaxed(match, clock->regbase + TIMER_MATCH_VAL);
	135	writel_relaxed(ctrl \| TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
3e4ea372 AH	136	return 0;
	137	}
	138
	139	static void msm_timer_set_mode(enum clock_event_mode mode,
	140	struct clock_event_device *evt)
	141	{
94790ec2	142	struct msm_clock *clock = clockevent_to_clock(evt);
a850c3f6 SB	143	u32 ctrl;
	144
	145	ctrl = readl_relaxed(clock->regbase + TIMER_ENABLE);
	146	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	147
3e4ea372 AH	148	switch (mode) {
	149	case CLOCK_EVT_MODE_RESUME:
	150	case CLOCK_EVT_MODE_PERIODIC:
	151	break;
	152	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	153	/* Timer is enabled in set_next_event */
3e4ea372 AH	154	break;
	155	case CLOCK_EVT_MODE_UNUSED:
	156	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	157	break;
3e4ea372 AH	158	}
a850c3f6	159	writel_relaxed(ctrl, clock->regbase + TIMER_ENABLE);
3e4ea372 AH	160	}
	161
	162	static struct msm_clock msm_clocks[] = {
94790ec2	163	[MSM_CLOCK_GPT] = {
3e4ea372 AH	164	.clockevent = {
	165	.name = "gp_timer",
	166	.features = CLOCK_EVT_FEAT_ONESHOT,
	167	.shift = 32,
	168	.rating = 200,
	169	.set_next_event = msm_timer_set_next_event,
	170	.set_mode = msm_timer_set_mode,
	171	},
28af690a	172	.irq = INT_GP_TIMER_EXP,
94790ec2	173	.freq = GPT_HZ,
3e4ea372	174	},
94790ec2	175	[MSM_CLOCK_DGT] = {
3e4ea372 AH	176	.clocksource = {
	177	.name = "dg_timer",
	178	.rating = 300,
94790ec2	179	.read = msm_read_timer_count,
3e4ea372	180	.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
3e4ea372 AH	181	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	182	},
3e4ea372	183	.freq = DGT_HZ >> MSM_DGT_SHIFT,
94790ec2	184	.shift = MSM_DGT_SHIFT,
3e4ea372 AH	185	}
	186	};
	187
	188	static void __init msm_timer_init(void)
	189	{
dd15ab81 SB	190	struct msm_clock *clock;
	191	struct clock_event_device *ce = &msm_clocks[MSM_CLOCK_GPT].clockevent;
	192	struct clocksource *cs = &msm_clocks[MSM_CLOCK_DGT].clocksource;
3e4ea372	193	int res;
8c27e6f3 DB	194	int global_offset = 0;
8c27e6f3 DB	195
dd15ab81	196
8c27e6f3 DB	197	if (cpu_is_msm7x01()) {
	198	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
	199	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
	200	} else if (cpu_is_msm7x30()) {
	201	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
	202	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
	203	} else if (cpu_is_qsd8x50()) {
	204	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
	205	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
a81c8c38	206	} else if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
8c27e6f3 DB	207	msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
	208	msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
	209
	210	/* Use CPU0's timer as the global timer. */
	211	global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
	212	} else
	213	BUG();
3e4ea372	214
94790ec2	215	#ifdef CONFIG_ARCH_MSM_SCORPIONMP
672039f0 JO	216	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	217	#endif
	218
dd15ab81 SB	219	clock = &msm_clocks[MSM_CLOCK_GPT];
dd15ab81 SB	220	clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
3e4ea372	221
dd15ab81 SB	222	writel_relaxed(0, clock->regbase + TIMER_ENABLE);
	223	writel_relaxed(0, clock->regbase + TIMER_CLEAR);
	224	writel_relaxed(~0, clock->regbase + TIMER_MATCH_VAL);
	225	ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
	226	/*
	227	* allow at least 10 seconds to notice that the timer
	228	* wrapped
	229	*/
	230	ce->max_delta_ns =
	231	clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
	232	/* 4 gets rounded down to 3 */
	233	ce->min_delta_ns = clockevent_delta2ns(4, ce);
	234	ce->cpumask = cpumask_of(0);
	235
	236	ce->irq = clock->irq;
	237	if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
	238	clock->percpu_evt = alloc_percpu(struct clock_event_device *);
	239	if (!clock->percpu_evt) {
	240	pr_err("memory allocation failed for %s\n", ce->name);
	241	goto err;
28af690a MZ	242	}
28af690a MZ	243
dd15ab81 SB	244	*__this_cpu_ptr(clock->percpu_evt) = ce;
	245	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
	246	ce->name, clock->percpu_evt);
	247	if (!res)
	248	enable_percpu_irq(ce->irq, 0);
	249	} else {
	250	clock->evt = ce;
	251	res = request_irq(ce->irq, msm_timer_interrupt,
	252	IRQF_TIMER \| IRQF_NOBALANCING \|
	253	IRQF_TRIGGER_RISING, ce->name, &clock->evt);
3e4ea372	254	}
dd15ab81 SB	255
	256	if (res)
	257	pr_err("request_irq failed for %s\n", ce->name);
	258
	259	clockevents_register_device(ce);
	260	err:
	261	clock = &msm_clocks[MSM_CLOCK_DGT];
	262	clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
	263	clock->global_counter = clock->local_counter + global_offset;
	264	writel_relaxed(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
	265	res = clocksource_register_hz(cs, clock->freq);
	266	if (res)
	267	pr_err("clocksource_register failed for %s\n", cs->name);
3e4ea372 AH	268	}
3e4ea372 AH	269
2852ccae	270	#ifdef CONFIG_LOCAL_TIMERS
af90f10d	271	int __cpuinit local_timer_setup(struct clock_event_device *evt)
94790ec2	272	{
28af690a	273	static bool local_timer_inited;
94790ec2 JO	274	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
	275
	276	/* Use existing clock_event for cpu 0 */
	277	if (!smp_processor_id())
893b66c3	278	return 0;
94790ec2	279
28af690a	280	if (!local_timer_inited) {
94790ec2 JO	281	writel(0, clock->regbase + TIMER_ENABLE);
	282	writel(0, clock->regbase + TIMER_CLEAR);
	283	writel(~0, clock->regbase + TIMER_MATCH_VAL);
28af690a	284	local_timer_inited = true;
94790ec2	285	}
28af690a	286	evt->irq = clock->irq;
94790ec2 JO	287	evt->name = "local_timer";
	288	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	289	evt->rating = clock->clockevent.rating;
	290	evt->set_mode = msm_timer_set_mode;
	291	evt->set_next_event = msm_timer_set_next_event;
	292	evt->shift = clock->clockevent.shift;
	293	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
	294	evt->max_delta_ns =
	295	clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
	296	evt->min_delta_ns = clockevent_delta2ns(4, evt);
	297
28af690a MZ	298	*__this_cpu_ptr(clock->percpu_evt) = evt;
28af690a MZ	299	enable_percpu_irq(evt->irq, 0);
94790ec2 JO	300
94790ec2 JO	301	clockevents_register_device(evt);
af90f10d	302	return 0;
94790ec2 JO	303	}
94790ec2 JO	304
28af690a	305	void local_timer_stop(struct clock_event_device *evt)
94790ec2	306	{
28af690a MZ	307	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
28af690a MZ	308	disable_percpu_irq(evt->irq);
94790ec2	309	}
2852ccae	310	#endif /* CONFIG_LOCAL_TIMERS */
94790ec2	311
3e4ea372 AH	312	struct sys_timer msm_timer = {
	313	.init = msm_timer_init
	314	};