[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <asm/hardware/gic.h>
#include <asm/localtimer.h>

#include <mach/msm_iomap.h>
#include <mach/cpu.h>
#include <mach/board.h>

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
#define TIMER_ENABLE_EN                 BIT(0)
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL             0x0034
#define DGT_CLK_CTL_DIV_4	0x3

#define GPT_HZ 32768

#define MSM_DGT_SHIFT 5

static void __iomem *event_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}

static struct clock_event_device msm_clockevent = {
	.name		= "gp_timer",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.rating		= 200,
	.set_next_event	= msm_timer_set_next_event,
	.set_mode	= msm_timer_set_mode,
};

static union {
	struct clock_event_device *evt;
	struct clock_event_device __percpu **percpu_evt;
} msm_evt;

static void __iomem *source_base;

static cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init msm_timer_init(void)
{
	struct clock_event_device *ce = &msm_clockevent;
	struct clocksource *cs = &msm_clocksource;
	int res;
	u32 dgt_hz;

	if (cpu_is_msm7x01()) {
		event_base = MSM_CSR_BASE;
		source_base = MSM_CSR_BASE + 0x10;
		dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
		cs->read = msm_read_timer_count_shift;
		cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	} else if (cpu_is_msm7x30()) {
		event_base = MSM_CSR_BASE + 0x04;
		source_base = MSM_CSR_BASE + 0x24;
		dgt_hz = 24576000 / 4;
	} else if (cpu_is_qsd8x50()) {
		event_base = MSM_CSR_BASE;
		source_base = MSM_CSR_BASE + 0x10;
		dgt_hz = 19200000 / 4;
	} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
		event_base = MSM_TMR_BASE + 0x04;
		/* Use CPU0's timer as the global clock source. */
		source_base = MSM_TMR0_BASE + 0x24;
		dgt_hz = 27000000 / 4;
		writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
	} else
		BUG();

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	ce->mult = div_sc(GPT_HZ, NSEC_PER_SEC, ce->shift);
	/*
	 * allow at least 10 seconds to notice that the timer
	 * wrapped
	 */
	ce->max_delta_ns = clockevent_delta2ns(0xf0000000, ce);
	/* 4 gets rounded down to 3 */
	ce->min_delta_ns = clockevent_delta2ns(4, ce);
	ce->cpumask = cpumask_of(0);

	ce->irq = INT_GP_TIMER_EXP;
	clockevents_register_device(ce);
	if (cpu_is_msm8x60() || cpu_is_msm8960()) {
		msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
		if (!msm_evt.percpu_evt) {
			pr_err("memory allocation failed for %s\n", ce->name);
			goto err;
		}
		*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
					 ce->name, msm_evt.percpu_evt);
		if (!res)
			enable_percpu_irq(ce->irq, 0);
	} else {
		msm_evt.evt = ce;
		res = request_irq(ce->irq, msm_timer_interrupt,
				  IRQF_TIMER | IRQF_NOBALANCING |
				  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
	}

	if (res)
		pr_err("request_irq failed for %s\n", ce->name);
err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
}

#ifdef CONFIG_LOCAL_TIMERS
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	evt->irq = msm_clockevent.irq;
	evt->name = "local_timer";
	evt->features = msm_clockevent.features;
	evt->rating = msm_clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;
	evt->shift = msm_clockevent.shift;
	evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
	evt->min_delta_ns = clockevent_delta2ns(4, evt);

	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
	clockevents_register_device(evt);
	enable_percpu_irq(evt->irq, 0);
	return 0;
}

void local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}
#endif /* CONFIG_LOCAL_TIMERS */

struct sys_timer msm_timer = {
	.init = msm_timer_init
};
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
dd15ab81	4	* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
3e4ea372	19	#include <linux/init.h>
3e4ea372 AH	20	#include <linux/interrupt.h>
3e4ea372 AH	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
3e4ea372 AH	23
3e4ea372 AH	24	#include <asm/mach/time.h>
ebf30dc9	25	#include <asm/hardware/gic.h>
4a184075	26	#include <asm/localtimer.h>
ebf30dc9	27
a09e64fb	28	#include <mach/msm_iomap.h>
8c27e6f3	29	#include <mach/cpu.h>
4a184075	30	#include <mach/board.h>
3e4ea372 AH	31
	32	#define TIMER_MATCH_VAL 0x0000
	33	#define TIMER_COUNT_VAL 0x0004
	34	#define TIMER_ENABLE 0x0008
4a184075 SB	35	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
4a184075 SB	36	#define TIMER_ENABLE_EN BIT(0)
3e4ea372	37	#define TIMER_CLEAR 0x000C
672039f0	38	#define DGT_CLK_CTL 0x0034
4a184075	39	#define DGT_CLK_CTL_DIV_4 0x3
3e4ea372 AH	40
3e4ea372 AH	41	#define GPT_HZ 32768
672039f0	42
2081a6b5	43	#define MSM_DGT_SHIFT 5
3e4ea372	44
2a00c106	45	static void __iomem *event_base;
a850c3f6	46
3e4ea372 AH	47	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	48	{
28af690a	49	struct clock_event_device evt = (struct clock_event_device **)dev_id;
a850c3f6 SB	50	/* Stop the timer tick */
a850c3f6 SB	51	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
2a00c106	52	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	53	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	54	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	55	}
3e4ea372 AH	56	evt->event_handler(evt);
	57	return IRQ_HANDLED;
	58	}
	59
3e4ea372 AH	60	static int msm_timer_set_next_event(unsigned long cycles,
	61	struct clock_event_device *evt)
	62	{
2a00c106	63	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	64
2a00c106 SB	65	writel_relaxed(0, event_base + TIMER_CLEAR);
	66	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	67	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	68	return 0;
	69	}
	70
	71	static void msm_timer_set_mode(enum clock_event_mode mode,
	72	struct clock_event_device *evt)
	73	{
a850c3f6 SB	74	u32 ctrl;
a850c3f6 SB	75
2a00c106	76	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	77	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	78
3e4ea372 AH	79	switch (mode) {
	80	case CLOCK_EVT_MODE_RESUME:
	81	case CLOCK_EVT_MODE_PERIODIC:
	82	break;
	83	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	84	/* Timer is enabled in set_next_event */
3e4ea372 AH	85	break;
	86	case CLOCK_EVT_MODE_UNUSED:
	87	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	88	break;
3e4ea372 AH	89	}
2a00c106	90	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
3e4ea372 AH	91	}
3e4ea372 AH	92
2a00c106 SB	93	static struct clock_event_device msm_clockevent = {
	94	.name = "gp_timer",
	95	.features = CLOCK_EVT_FEAT_ONESHOT,
	96	.shift = 32,
	97	.rating = 200,
	98	.set_next_event = msm_timer_set_next_event,
	99	.set_mode = msm_timer_set_mode,
	100	};
	101
	102	static union {
	103	struct clock_event_device *evt;
	104	struct clock_event_device __percpu **percpu_evt;
	105	} msm_evt;
	106
	107	static void __iomem *source_base;
	108
	109	static cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	110	{
	111	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	112	}
	113
	114	static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
2a00c106 SB	115	{
	116	/*
	117	* Shift timer count down by a constant due to unreliable lower bits
	118	* on some targets.
	119	*/
2081a6b5	120	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
2a00c106 SB	121	}
	122
	123	static struct clocksource msm_clocksource = {
	124	.name = "dg_timer",
	125	.rating = 300,
	126	.read = msm_read_timer_count,
2081a6b5	127	.mask = CLOCKSOURCE_MASK(32),
2a00c106	128	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	129	};
	130
	131	static void __init msm_timer_init(void)
	132	{
2a00c106 SB	133	struct clock_event_device *ce = &msm_clockevent;
2a00c106 SB	134	struct clocksource *cs = &msm_clocksource;
3e4ea372	135	int res;
2081a6b5	136	u32 dgt_hz;
dd15ab81	137
8c27e6f3	138	if (cpu_is_msm7x01()) {
2a00c106 SB	139	event_base = MSM_CSR_BASE;
2a00c106 SB	140	source_base = MSM_CSR_BASE + 0x10;
2081a6b5 SB	141	dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
	142	cs->read = msm_read_timer_count_shift;
	143	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
8c27e6f3	144	} else if (cpu_is_msm7x30()) {
2a00c106 SB	145	event_base = MSM_CSR_BASE + 0x04;
2a00c106 SB	146	source_base = MSM_CSR_BASE + 0x24;
2081a6b5	147	dgt_hz = 24576000 / 4;
8c27e6f3	148	} else if (cpu_is_qsd8x50()) {
2a00c106 SB	149	event_base = MSM_CSR_BASE;
2a00c106 SB	150	source_base = MSM_CSR_BASE + 0x10;
2081a6b5	151	dgt_hz = 19200000 / 4;
a81c8c38	152	} else if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
2a00c106 SB	153	event_base = MSM_TMR_BASE + 0x04;
	154	/* Use CPU0's timer as the global clock source. */
	155	source_base = MSM_TMR0_BASE + 0x24;
2081a6b5 SB	156	dgt_hz = 27000000 / 4;
2081a6b5 SB	157	writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
8c27e6f3 DB	158	} else
8c27e6f3 DB	159	BUG();
3e4ea372	160
2a00c106 SB	161	writel_relaxed(0, event_base + TIMER_ENABLE);
	162	writel_relaxed(0, event_base + TIMER_CLEAR);
	163	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	164	ce->mult = div_sc(GPT_HZ, NSEC_PER_SEC, ce->shift);
dd15ab81 SB	165	/*
	166	* allow at least 10 seconds to notice that the timer
	167	* wrapped
	168	*/
2a00c106	169	ce->max_delta_ns = clockevent_delta2ns(0xf0000000, ce);
dd15ab81 SB	170	/* 4 gets rounded down to 3 */
	171	ce->min_delta_ns = clockevent_delta2ns(4, ce);
	172	ce->cpumask = cpumask_of(0);
	173
2a00c106	174	ce->irq = INT_GP_TIMER_EXP;
dde7d61e	175	clockevents_register_device(ce);
dd15ab81	176	if (cpu_is_msm8x60() \|\| cpu_is_msm8960()) {
2a00c106 SB	177	msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
2a00c106 SB	178	if (!msm_evt.percpu_evt) {
dd15ab81 SB	179	pr_err("memory allocation failed for %s\n", ce->name);
dd15ab81 SB	180	goto err;
28af690a	181	}
2a00c106	182	*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
dd15ab81	183	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
2a00c106	184	ce->name, msm_evt.percpu_evt);
dd15ab81 SB	185	if (!res)
	186	enable_percpu_irq(ce->irq, 0);
	187	} else {
2a00c106	188	msm_evt.evt = ce;
dd15ab81 SB	189	res = request_irq(ce->irq, msm_timer_interrupt,
dd15ab81 SB	190	IRQF_TIMER \| IRQF_NOBALANCING \|
2a00c106	191	IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
3e4ea372	192	}
dd15ab81 SB	193
	194	if (res)
	195	pr_err("request_irq failed for %s\n", ce->name);
dd15ab81	196	err:
2a00c106	197	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	198	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	199	if (res)
2a00c106	200	pr_err("clocksource_register failed\n");
3e4ea372 AH	201	}
3e4ea372 AH	202
2852ccae	203	#ifdef CONFIG_LOCAL_TIMERS
af90f10d	204	int __cpuinit local_timer_setup(struct clock_event_device *evt)
94790ec2	205	{
94790ec2 JO	206	/* Use existing clock_event for cpu 0 */
94790ec2 JO	207	if (!smp_processor_id())
893b66c3	208	return 0;
94790ec2	209
2a00c106 SB	210	writel_relaxed(0, event_base + TIMER_ENABLE);
	211	writel_relaxed(0, event_base + TIMER_CLEAR);
	212	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	213	evt->irq = msm_clockevent.irq;
94790ec2	214	evt->name = "local_timer";
2a00c106 SB	215	evt->features = msm_clockevent.features;
2a00c106 SB	216	evt->rating = msm_clockevent.rating;
94790ec2 JO	217	evt->set_mode = msm_timer_set_mode;
94790ec2 JO	218	evt->set_next_event = msm_timer_set_next_event;
2a00c106 SB	219	evt->shift = msm_clockevent.shift;
	220	evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
	221	evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
94790ec2 JO	222	evt->min_delta_ns = clockevent_delta2ns(4, evt);
94790ec2 JO	223
2a00c106	224	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
94790ec2	225	clockevents_register_device(evt);
dde7d61e	226	enable_percpu_irq(evt->irq, 0);
af90f10d	227	return 0;
94790ec2 JO	228	}
94790ec2 JO	229
28af690a	230	void local_timer_stop(struct clock_event_device *evt)
94790ec2	231	{
28af690a MZ	232	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
28af690a MZ	233	disable_percpu_irq(evt->irq);
94790ec2	234	}
2852ccae	235	#endif /* CONFIG_LOCAL_TIMERS */
94790ec2	236
3e4ea372 AH	237	struct sys_timer msm_timer = {
	238	.init = msm_timer_init
	239	};