[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/mach/time.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>

#include "common.h"

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
#define TIMER_ENABLE_EN                 BIT(0)
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL		0x10
#define DGT_CLK_CTL_DIV_4	0x3

#define GPT_HZ 32768

#define MSM_DGT_SHIFT 5

static void __iomem *event_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}

static struct clock_event_device msm_clockevent = {
	.name		= "gp_timer",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= msm_timer_set_next_event,
	.set_mode	= msm_timer_set_mode,
};

static union {
	struct clock_event_device *evt;
	struct clock_event_device * __percpu *percpu_evt;
} msm_evt;

static void __iomem *source_base;

static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

#ifdef CONFIG_LOCAL_TIMERS
static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
{
	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	evt->irq = msm_clockevent.irq;
	evt->name = "local_timer";
	evt->features = msm_clockevent.features;
	evt->rating = msm_clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;

	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void msm_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}

static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
	.setup	= msm_local_timer_setup,
	.stop	= msm_local_timer_stop,
};
#endif /* CONFIG_LOCAL_TIMERS */

static notrace u32 msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clock_event_device *ce = &msm_clockevent;
	struct clocksource *cs = &msm_clocksource;
	int res;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	ce->cpumask = cpumask_of(0);
	ce->irq = irq;

	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
	if (percpu) {
		msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
		if (!msm_evt.percpu_evt) {
			pr_err("memory allocation failed for %s\n", ce->name);
			goto err;
		}
		*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
					 ce->name, msm_evt.percpu_evt);
		if (!res) {
			enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_LOCAL_TIMERS
			local_timer_register(&msm_local_timer_ops);
#endif
		}
	} else {
		msm_evt.evt = ce;
		res = request_irq(ce->irq, msm_timer_interrupt,
				  IRQF_TIMER | IRQF_NOBALANCING |
				  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
	}

	if (res)
		pr_err("request_irq failed for %s\n", ce->name);
err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
}

#ifdef CONFIG_OF
static const struct of_device_id msm_timer_match[] __initconst = {
	{ .compatible = "qcom,kpss-timer" },
	{ .compatible = "qcom,scss-timer" },
	{ },
};

void __init msm_dt_timer_init(void)
{
	struct device_node *np;
	u32 freq;
	int irq;
	struct resource res;
	u32 percpu_offset;
	void __iomem *base;
	void __iomem *cpu0_base;

	np = of_find_matching_node(NULL, msm_timer_match);
	if (!np) {
		pr_err("Can't find msm timer DT node\n");
		return;
	}

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to map event base\n");
		return;
	}

	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return;
	}

	/* We use CPU0's DGT for the clocksource */
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("Failed to parse DGT resource\n");
		return;
	}

	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
		pr_err("Failed to map source base\n");
		return;
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return;
	}
	of_node_put(np);

	event_base = base + 0x4;
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

	msm_timer_init(freq, 32, irq, !!percpu_offset);
}
#endif

static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source)
{
	void __iomem *base;

	base = ioremap(addr, SZ_256);
	if (!base) {
		pr_err("Failed to map timer base\n");
		return -ENOMEM;
	}
	event_base = base + event;
	source_base = base + source;

	return 0;
}

void __init msm7x01_timer_init(void)
{
	struct clocksource *cs = &msm_clocksource;

	if (msm_timer_map(0xc0100000, 0x0, 0x10))
		return;
	cs->read = msm_read_timer_count_shift;
	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	/* 600 KHz */
	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
			false);
}

void __init msm7x30_timer_init(void)
{
	if (msm_timer_map(0xc0100000, 0x4, 0x24))
		return;
	msm_timer_init(24576000 / 4, 32, 1, false);
}

void __init qsd8x50_timer_init(void)
{
	if (msm_timer_map(0xAC100000, 0x0, 0x10))
		return;
	msm_timer_init(19200000 / 4, 32, 7, false);
}
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
4312a7ef	4	* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
3e4ea372	19	#include <linux/init.h>
3e4ea372 AH	20	#include <linux/interrupt.h>
3e4ea372 AH	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
6e332163 SB	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
3e4ea372 AH	26
3e4ea372 AH	27	#include <asm/mach/time.h>
4a184075	28	#include <asm/localtimer.h>
f8e56c42	29	#include <asm/sched_clock.h>
ebf30dc9	30
4312a7ef	31	#include "common.h"
3e4ea372 AH	32
	33	#define TIMER_MATCH_VAL 0x0000
	34	#define TIMER_COUNT_VAL 0x0004
	35	#define TIMER_ENABLE 0x0008
4a184075 SB	36	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
4a184075 SB	37	#define TIMER_ENABLE_EN BIT(0)
3e4ea372	38	#define TIMER_CLEAR 0x000C
eebdb0c1	39	#define DGT_CLK_CTL 0x10
4a184075	40	#define DGT_CLK_CTL_DIV_4 0x3
3e4ea372 AH	41
3e4ea372 AH	42	#define GPT_HZ 32768
672039f0	43
2081a6b5	44	#define MSM_DGT_SHIFT 5
3e4ea372	45
2a00c106	46	static void __iomem *event_base;
a850c3f6	47
3e4ea372 AH	48	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	49	{
28af690a	50	struct clock_event_device evt = (struct clock_event_device **)dev_id;
a850c3f6 SB	51	/* Stop the timer tick */
a850c3f6 SB	52	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
2a00c106	53	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	54	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	55	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	56	}
3e4ea372 AH	57	evt->event_handler(evt);
	58	return IRQ_HANDLED;
	59	}
	60
3e4ea372 AH	61	static int msm_timer_set_next_event(unsigned long cycles,
	62	struct clock_event_device *evt)
	63	{
2a00c106	64	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	65
2a00c106 SB	66	writel_relaxed(0, event_base + TIMER_CLEAR);
	67	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	68	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	69	return 0;
	70	}
	71
	72	static void msm_timer_set_mode(enum clock_event_mode mode,
	73	struct clock_event_device *evt)
	74	{
a850c3f6 SB	75	u32 ctrl;
a850c3f6 SB	76
2a00c106	77	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	78	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	79
3e4ea372 AH	80	switch (mode) {
	81	case CLOCK_EVT_MODE_RESUME:
	82	case CLOCK_EVT_MODE_PERIODIC:
	83	break;
	84	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	85	/* Timer is enabled in set_next_event */
3e4ea372 AH	86	break;
	87	case CLOCK_EVT_MODE_UNUSED:
	88	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	89	break;
3e4ea372 AH	90	}
2a00c106	91	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
3e4ea372 AH	92	}
3e4ea372 AH	93
2a00c106 SB	94	static struct clock_event_device msm_clockevent = {
	95	.name = "gp_timer",
	96	.features = CLOCK_EVT_FEAT_ONESHOT,
2a00c106 SB	97	.rating = 200,
	98	.set_next_event = msm_timer_set_next_event,
	99	.set_mode = msm_timer_set_mode,
	100	};
	101
	102	static union {
	103	struct clock_event_device *evt;
3b5909de	104	struct clock_event_device * __percpu *percpu_evt;
2a00c106 SB	105	} msm_evt;
	106
	107	static void __iomem *source_base;
	108
f8e56c42	109	static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	110	{
	111	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	112	}
	113
f8e56c42	114	static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
2a00c106 SB	115	{
	116	/*
	117	* Shift timer count down by a constant due to unreliable lower bits
	118	* on some targets.
	119	*/
2081a6b5	120	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
2a00c106 SB	121	}
	122
	123	static struct clocksource msm_clocksource = {
	124	.name = "dg_timer",
	125	.rating = 300,
	126	.read = msm_read_timer_count,
2081a6b5	127	.mask = CLOCKSOURCE_MASK(32),
2a00c106	128	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	129	};
3e4ea372 AH	130
5ca709c1 MZ	131	#ifdef CONFIG_LOCAL_TIMERS
	132	static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
	133	{
	134	/* Use existing clock_event for cpu 0 */
	135	if (!smp_processor_id())
	136	return 0;
	137
	138	writel_relaxed(0, event_base + TIMER_ENABLE);
	139	writel_relaxed(0, event_base + TIMER_CLEAR);
	140	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	141	evt->irq = msm_clockevent.irq;
	142	evt->name = "local_timer";
	143	evt->features = msm_clockevent.features;
	144	evt->rating = msm_clockevent.rating;
	145	evt->set_mode = msm_timer_set_mode;
	146	evt->set_next_event = msm_timer_set_next_event;
5ca709c1 MZ	147
5ca709c1 MZ	148	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
838a2ae8	149	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
66a89509	150	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	151	return 0;
	152	}
	153
	154	static void msm_local_timer_stop(struct clock_event_device *evt)
	155	{
	156	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	157	disable_percpu_irq(evt->irq);
	158	}
	159
	160	static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
	161	.setup = msm_local_timer_setup,
	162	.stop = msm_local_timer_stop,
	163	};
	164	#endif /* CONFIG_LOCAL_TIMERS */
	165
f8e56c42 SB	166	static notrace u32 msm_sched_clock_read(void)
	167	{
	168	return msm_clocksource.read(&msm_clocksource);
	169	}
	170
4312a7ef SB	171	static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef SB	172	bool percpu)
3e4ea372	173	{
2a00c106 SB	174	struct clock_event_device *ce = &msm_clockevent;
2a00c106 SB	175	struct clocksource *cs = &msm_clocksource;
3e4ea372 AH	176	int res;
3e4ea372 AH	177
2a00c106 SB	178	writel_relaxed(0, event_base + TIMER_ENABLE);
	179	writel_relaxed(0, event_base + TIMER_CLEAR);
	180	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
dd15ab81	181	ce->cpumask = cpumask_of(0);
4312a7ef	182	ce->irq = irq;
dd15ab81	183
27fdb577	184	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
4312a7ef	185	if (percpu) {
2a00c106 SB	186	msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
2a00c106 SB	187	if (!msm_evt.percpu_evt) {
dd15ab81 SB	188	pr_err("memory allocation failed for %s\n", ce->name);
dd15ab81 SB	189	goto err;
28af690a	190	}
2a00c106	191	*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
dd15ab81	192	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
2a00c106	193	ce->name, msm_evt.percpu_evt);
5ca709c1	194	if (!res) {
66a89509	195	enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	196	#ifdef CONFIG_LOCAL_TIMERS
	197	local_timer_register(&msm_local_timer_ops);
	198	#endif
	199	}
dd15ab81	200	} else {
2a00c106	201	msm_evt.evt = ce;
dd15ab81 SB	202	res = request_irq(ce->irq, msm_timer_interrupt,
dd15ab81 SB	203	IRQF_TIMER \| IRQF_NOBALANCING \|
2a00c106	204	IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
3e4ea372	205	}
dd15ab81 SB	206
	207	if (res)
	208	pr_err("request_irq failed for %s\n", ce->name);
dd15ab81	209	err:
2a00c106	210	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	211	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	212	if (res)
2a00c106	213	pr_err("clocksource_register failed\n");
4312a7ef	214	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
3e4ea372 AH	215	}
3e4ea372 AH	216
6e332163	217	#ifdef CONFIG_OF
eebdb0c1 SB	218	static const struct of_device_id msm_timer_match[] __initconst = {
	219	{ .compatible = "qcom,kpss-timer" },
	220	{ .compatible = "qcom,scss-timer" },
6e332163 SB	221	{ },
	222	};
	223
6bb27d73	224	void __init msm_dt_timer_init(void)
6e332163 SB	225	{
	226	struct device_node *np;
	227	u32 freq;
	228	int irq;
	229	struct resource res;
	230	u32 percpu_offset;
eebdb0c1 SB	231	void __iomem *base;
eebdb0c1 SB	232	void __iomem *cpu0_base;
6e332163	233
eebdb0c1	234	np = of_find_matching_node(NULL, msm_timer_match);
6e332163	235	if (!np) {
eebdb0c1	236	pr_err("Can't find msm timer DT node\n");
6e332163 SB	237	return;
	238	}
	239
eebdb0c1 SB	240	base = of_iomap(np, 0);
eebdb0c1 SB	241	if (!base) {
6e332163 SB	242	pr_err("Failed to map event base\n");
	243	return;
	244	}
	245
eebdb0c1 SB	246	/* We use GPT0 for the clockevent */
eebdb0c1 SB	247	irq = irq_of_parse_and_map(np, 1);
6e332163 SB	248	if (irq <= 0) {
	249	pr_err("Can't get irq\n");
	250	return;
	251	}
6e332163	252
eebdb0c1	253	/* We use CPU0's DGT for the clocksource */
6e332163 SB	254	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	255	percpu_offset = 0;
	256
	257	if (of_address_to_resource(np, 0, &res)) {
	258	pr_err("Failed to parse DGT resource\n");
	259	return;
	260	}
	261
eebdb0c1 SB	262	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
eebdb0c1 SB	263	if (!cpu0_base) {
6e332163 SB	264	pr_err("Failed to map source base\n");
	265	return;
	266	}
	267
6e332163 SB	268	if (of_property_read_u32(np, "clock-frequency", &freq)) {
	269	pr_err("Unknown frequency\n");
	270	return;
	271	}
	272	of_node_put(np);
	273
eebdb0c1 SB	274	event_base = base + 0x4;
	275	source_base = cpu0_base + 0x24;
	276	freq /= 4;
	277	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
	278
6e332163 SB	279	msm_timer_init(freq, 32, irq, !!percpu_offset);
6e332163 SB	280	}
6e332163 SB	281	#endif
6e332163 SB	282
eebdb0c1	283	static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source)
4312a7ef	284	{
eebdb0c1 SB	285	void __iomem *base;
	286
	287	base = ioremap(addr, SZ_256);
	288	if (!base) {
	289	pr_err("Failed to map timer base\n");
	290	return -ENOMEM;
4312a7ef	291	}
eebdb0c1 SB	292	event_base = base + event;
	293	source_base = base + source;
	294
4312a7ef SB	295	return 0;
	296	}
	297
6bb27d73	298	void __init msm7x01_timer_init(void)
4312a7ef SB	299	{
	300	struct clocksource *cs = &msm_clocksource;
	301
eebdb0c1	302	if (msm_timer_map(0xc0100000, 0x0, 0x10))
4312a7ef SB	303	return;
	304	cs->read = msm_read_timer_count_shift;
	305	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	306	/* 600 KHz */
	307	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
	308	false);
	309	}
	310
6bb27d73	311	void __init msm7x30_timer_init(void)
4312a7ef	312	{
eebdb0c1	313	if (msm_timer_map(0xc0100000, 0x4, 0x24))
4312a7ef SB	314	return;
	315	msm_timer_init(24576000 / 4, 32, 1, false);
	316	}
	317
6bb27d73	318	void __init qsd8x50_timer_init(void)
4312a7ef	319	{
eebdb0c1	320	if (msm_timer_map(0xAC100000, 0x0, 0x10))
4312a7ef SB	321	return;
	322	msm_timer_init(19200000 / 4, 32, 7, false);
	323	}