[deliverable/linux.git] / arch / arm / mach-msm / timer.c

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/mach/time.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>

#include "common.h"

#define TIMER_MATCH_VAL         0x0000
#define TIMER_COUNT_VAL         0x0004
#define TIMER_ENABLE            0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
#define TIMER_ENABLE_EN                 BIT(0)
#define TIMER_CLEAR             0x000C
#define DGT_CLK_CTL_DIV_4	0x3

#define GPT_HZ 32768

#define MSM_DGT_SHIFT 5

static void __iomem *event_base;

static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
	/* Stop the timer tick */
	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
		ctrl &= ~TIMER_ENABLE_EN;
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
	}
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);

	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
	return 0;
}

static void msm_timer_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	u32 ctrl;

	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);

	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Timer is enabled in set_next_event */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;
	}
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}

static struct clock_event_device msm_clockevent = {
	.name		= "gp_timer",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= msm_timer_set_next_event,
	.set_mode	= msm_timer_set_mode,
};

static union {
	struct clock_event_device *evt;
	struct clock_event_device * __percpu *percpu_evt;
} msm_evt;

static void __iomem *source_base;

static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
	/*
	 * Shift timer count down by a constant due to unreliable lower bits
	 * on some targets.
	 */
	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}

static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

#ifdef CONFIG_LOCAL_TIMERS
static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
{
	/* Use existing clock_event for cpu 0 */
	if (!smp_processor_id())
		return 0;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	evt->irq = msm_clockevent.irq;
	evt->name = "local_timer";
	evt->features = msm_clockevent.features;
	evt->rating = msm_clockevent.rating;
	evt->set_mode = msm_timer_set_mode;
	evt->set_next_event = msm_timer_set_next_event;

	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void msm_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	disable_percpu_irq(evt->irq);
}

static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
	.setup	= msm_local_timer_setup,
	.stop	= msm_local_timer_stop,
};
#endif /* CONFIG_LOCAL_TIMERS */

static notrace u32 msm_sched_clock_read(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
				  bool percpu)
{
	struct clock_event_device *ce = &msm_clockevent;
	struct clocksource *cs = &msm_clocksource;
	int res;

	writel_relaxed(0, event_base + TIMER_ENABLE);
	writel_relaxed(0, event_base + TIMER_CLEAR);
	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	ce->cpumask = cpumask_of(0);
	ce->irq = irq;

	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
	if (percpu) {
		msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
		if (!msm_evt.percpu_evt) {
			pr_err("memory allocation failed for %s\n", ce->name);
			goto err;
		}
		*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
		res = request_percpu_irq(ce->irq, msm_timer_interrupt,
					 ce->name, msm_evt.percpu_evt);
		if (!res) {
			enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_LOCAL_TIMERS
			local_timer_register(&msm_local_timer_ops);
#endif
		}
	} else {
		msm_evt.evt = ce;
		res = request_irq(ce->irq, msm_timer_interrupt,
				  IRQF_TIMER | IRQF_NOBALANCING |
				  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
	}

	if (res)
		pr_err("request_irq failed for %s\n", ce->name);
err:
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
	res = clocksource_register_hz(cs, dgt_hz);
	if (res)
		pr_err("clocksource_register failed\n");
	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
}

#ifdef CONFIG_OF
static const struct of_device_id msm_dgt_match[] __initconst = {
	{ .compatible = "qcom,msm-dgt" },
	{ },
};

static const struct of_device_id msm_gpt_match[] __initconst = {
	{ .compatible = "qcom,msm-gpt" },
	{ },
};

void __init msm_dt_timer_init(void)
{
	struct device_node *np;
	u32 freq;
	int irq;
	struct resource res;
	u32 percpu_offset;
	void __iomem *dgt_clk_ctl;

	np = of_find_matching_node(NULL, msm_gpt_match);
	if (!np) {
		pr_err("Can't find GPT DT node\n");
		return;
	}

	event_base = of_iomap(np, 0);
	if (!event_base) {
		pr_err("Failed to map event base\n");
		return;
	}

	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_err("Can't get irq\n");
		return;
	}
	of_node_put(np);

	np = of_find_matching_node(NULL, msm_dgt_match);
	if (!np) {
		pr_err("Can't find DGT DT node\n");
		return;
	}

	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("Failed to parse DGT resource\n");
		return;
	}

	source_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!source_base) {
		pr_err("Failed to map source base\n");
		return;
	}

	if (!of_address_to_resource(np, 1, &res)) {
		dgt_clk_ctl = ioremap(res.start + percpu_offset,
				      resource_size(&res));
		if (!dgt_clk_ctl) {
			pr_err("Failed to map DGT control base\n");
			return;
		}
		writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
		iounmap(dgt_clk_ctl);
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
		return;
	}
	of_node_put(np);

	msm_timer_init(freq, 32, irq, !!percpu_offset);
}
#endif

static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
{
	event_base = ioremap(event, SZ_64);
	if (!event_base) {
		pr_err("Failed to map event base\n");
		return 1;
	}
	source_base = ioremap(source, SZ_64);
	if (!source_base) {
		pr_err("Failed to map source base\n");
		return 1;
	}
	return 0;
}

void __init msm7x01_timer_init(void)
{
	struct clocksource *cs = &msm_clocksource;

	if (msm_timer_map(0xc0100000, 0xc0100010))
		return;
	cs->read = msm_read_timer_count_shift;
	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	/* 600 KHz */
	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
			false);
}

void __init msm7x30_timer_init(void)
{
	if (msm_timer_map(0xc0100004, 0xc0100024))
		return;
	msm_timer_init(24576000 / 4, 32, 1, false);
}

void __init qsd8x50_timer_init(void)
{
	if (msm_timer_map(0xAC100000, 0xAC100010))
		return;
	msm_timer_init(19200000 / 4, 32, 7, false);
}
Commit	Line	Data
dd15ab81	1	/*
3e4ea372 AH	2	*
3e4ea372 AH	3	* Copyright (C) 2007 Google, Inc.
4312a7ef	4	* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
3e4ea372 AH	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
4a184075 SB	17	#include <linux/clocksource.h>
4a184075 SB	18	#include <linux/clockchips.h>
3e4ea372	19	#include <linux/init.h>
3e4ea372 AH	20	#include <linux/interrupt.h>
3e4ea372 AH	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
6e332163 SB	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
3e4ea372 AH	26
3e4ea372 AH	27	#include <asm/mach/time.h>
4a184075	28	#include <asm/localtimer.h>
f8e56c42	29	#include <asm/sched_clock.h>
ebf30dc9	30
4312a7ef	31	#include "common.h"
3e4ea372 AH	32
	33	#define TIMER_MATCH_VAL 0x0000
	34	#define TIMER_COUNT_VAL 0x0004
	35	#define TIMER_ENABLE 0x0008
4a184075 SB	36	#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
4a184075 SB	37	#define TIMER_ENABLE_EN BIT(0)
3e4ea372	38	#define TIMER_CLEAR 0x000C
4a184075	39	#define DGT_CLK_CTL_DIV_4 0x3
3e4ea372 AH	40
3e4ea372 AH	41	#define GPT_HZ 32768
672039f0	42
2081a6b5	43	#define MSM_DGT_SHIFT 5
3e4ea372	44
2a00c106	45	static void __iomem *event_base;
a850c3f6	46
3e4ea372 AH	47	static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
3e4ea372 AH	48	{
28af690a	49	struct clock_event_device evt = (struct clock_event_device **)dev_id;
a850c3f6 SB	50	/* Stop the timer tick */
a850c3f6 SB	51	if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
2a00c106	52	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	53	ctrl &= ~TIMER_ENABLE_EN;
2a00c106	54	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
a850c3f6	55	}
3e4ea372 AH	56	evt->event_handler(evt);
	57	return IRQ_HANDLED;
	58	}
	59
3e4ea372 AH	60	static int msm_timer_set_next_event(unsigned long cycles,
	61	struct clock_event_device *evt)
	62	{
2a00c106	63	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
3e4ea372	64
2a00c106 SB	65	writel_relaxed(0, event_base + TIMER_CLEAR);
	66	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
	67	writel_relaxed(ctrl \| TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
3e4ea372 AH	68	return 0;
	69	}
	70
	71	static void msm_timer_set_mode(enum clock_event_mode mode,
	72	struct clock_event_device *evt)
	73	{
a850c3f6 SB	74	u32 ctrl;
a850c3f6 SB	75
2a00c106	76	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
a850c3f6	77	ctrl &= ~(TIMER_ENABLE_EN \| TIMER_ENABLE_CLR_ON_MATCH_EN);
94790ec2	78
3e4ea372 AH	79	switch (mode) {
	80	case CLOCK_EVT_MODE_RESUME:
	81	case CLOCK_EVT_MODE_PERIODIC:
	82	break;
	83	case CLOCK_EVT_MODE_ONESHOT:
a850c3f6	84	/* Timer is enabled in set_next_event */
3e4ea372 AH	85	break;
	86	case CLOCK_EVT_MODE_UNUSED:
	87	case CLOCK_EVT_MODE_SHUTDOWN:
3e4ea372 AH	88	break;
3e4ea372 AH	89	}
2a00c106	90	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
3e4ea372 AH	91	}
3e4ea372 AH	92
2a00c106 SB	93	static struct clock_event_device msm_clockevent = {
	94	.name = "gp_timer",
	95	.features = CLOCK_EVT_FEAT_ONESHOT,
2a00c106 SB	96	.rating = 200,
	97	.set_next_event = msm_timer_set_next_event,
	98	.set_mode = msm_timer_set_mode,
	99	};
	100
	101	static union {
	102	struct clock_event_device *evt;
3b5909de	103	struct clock_event_device * __percpu *percpu_evt;
2a00c106 SB	104	} msm_evt;
	105
	106	static void __iomem *source_base;
	107
f8e56c42	108	static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
2081a6b5 SB	109	{
	110	return readl_relaxed(source_base + TIMER_COUNT_VAL);
	111	}
	112
f8e56c42	113	static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
2a00c106 SB	114	{
	115	/*
	116	* Shift timer count down by a constant due to unreliable lower bits
	117	* on some targets.
	118	*/
2081a6b5	119	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
2a00c106 SB	120	}
	121
	122	static struct clocksource msm_clocksource = {
	123	.name = "dg_timer",
	124	.rating = 300,
	125	.read = msm_read_timer_count,
2081a6b5	126	.mask = CLOCKSOURCE_MASK(32),
2a00c106	127	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
3e4ea372 AH	128	};
3e4ea372 AH	129
5ca709c1 MZ	130	#ifdef CONFIG_LOCAL_TIMERS
	131	static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
	132	{
	133	/* Use existing clock_event for cpu 0 */
	134	if (!smp_processor_id())
	135	return 0;
	136
	137	writel_relaxed(0, event_base + TIMER_ENABLE);
	138	writel_relaxed(0, event_base + TIMER_CLEAR);
	139	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
	140	evt->irq = msm_clockevent.irq;
	141	evt->name = "local_timer";
	142	evt->features = msm_clockevent.features;
	143	evt->rating = msm_clockevent.rating;
	144	evt->set_mode = msm_timer_set_mode;
	145	evt->set_next_event = msm_timer_set_next_event;
5ca709c1 MZ	146
5ca709c1 MZ	147	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
838a2ae8	148	clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
66a89509	149	enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	150	return 0;
	151	}
	152
	153	static void msm_local_timer_stop(struct clock_event_device *evt)
	154	{
	155	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	156	disable_percpu_irq(evt->irq);
	157	}
	158
	159	static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
	160	.setup = msm_local_timer_setup,
	161	.stop = msm_local_timer_stop,
	162	};
	163	#endif /* CONFIG_LOCAL_TIMERS */
	164
f8e56c42 SB	165	static notrace u32 msm_sched_clock_read(void)
	166	{
	167	return msm_clocksource.read(&msm_clocksource);
	168	}
	169
4312a7ef SB	170	static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
4312a7ef SB	171	bool percpu)
3e4ea372	172	{
2a00c106 SB	173	struct clock_event_device *ce = &msm_clockevent;
2a00c106 SB	174	struct clocksource *cs = &msm_clocksource;
3e4ea372 AH	175	int res;
3e4ea372 AH	176
2a00c106 SB	177	writel_relaxed(0, event_base + TIMER_ENABLE);
	178	writel_relaxed(0, event_base + TIMER_CLEAR);
	179	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
dd15ab81	180	ce->cpumask = cpumask_of(0);
4312a7ef	181	ce->irq = irq;
dd15ab81	182
27fdb577	183	clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
4312a7ef	184	if (percpu) {
2a00c106 SB	185	msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
2a00c106 SB	186	if (!msm_evt.percpu_evt) {
dd15ab81 SB	187	pr_err("memory allocation failed for %s\n", ce->name);
dd15ab81 SB	188	goto err;
28af690a	189	}
2a00c106	190	*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
dd15ab81	191	res = request_percpu_irq(ce->irq, msm_timer_interrupt,
2a00c106	192	ce->name, msm_evt.percpu_evt);
5ca709c1	193	if (!res) {
66a89509	194	enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
5ca709c1 MZ	195	#ifdef CONFIG_LOCAL_TIMERS
	196	local_timer_register(&msm_local_timer_ops);
	197	#endif
	198	}
dd15ab81	199	} else {
2a00c106	200	msm_evt.evt = ce;
dd15ab81 SB	201	res = request_irq(ce->irq, msm_timer_interrupt,
dd15ab81 SB	202	IRQF_TIMER \| IRQF_NOBALANCING \|
2a00c106	203	IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
3e4ea372	204	}
dd15ab81 SB	205
	206	if (res)
	207	pr_err("request_irq failed for %s\n", ce->name);
dd15ab81	208	err:
2a00c106	209	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
2081a6b5	210	res = clocksource_register_hz(cs, dgt_hz);
dd15ab81	211	if (res)
2a00c106	212	pr_err("clocksource_register failed\n");
4312a7ef	213	setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
3e4ea372 AH	214	}
3e4ea372 AH	215
6e332163 SB	216	#ifdef CONFIG_OF
	217	static const struct of_device_id msm_dgt_match[] __initconst = {
	218	{ .compatible = "qcom,msm-dgt" },
	219	{ },
	220	};
	221
	222	static const struct of_device_id msm_gpt_match[] __initconst = {
	223	{ .compatible = "qcom,msm-gpt" },
	224	{ },
	225	};
	226
6bb27d73	227	void __init msm_dt_timer_init(void)
6e332163 SB	228	{
	229	struct device_node *np;
	230	u32 freq;
	231	int irq;
	232	struct resource res;
	233	u32 percpu_offset;
	234	void __iomem *dgt_clk_ctl;
	235
	236	np = of_find_matching_node(NULL, msm_gpt_match);
	237	if (!np) {
	238	pr_err("Can't find GPT DT node\n");
	239	return;
	240	}
	241
	242	event_base = of_iomap(np, 0);
	243	if (!event_base) {
	244	pr_err("Failed to map event base\n");
	245	return;
	246	}
	247
	248	irq = irq_of_parse_and_map(np, 0);
	249	if (irq <= 0) {
	250	pr_err("Can't get irq\n");
	251	return;
	252	}
	253	of_node_put(np);
	254
	255	np = of_find_matching_node(NULL, msm_dgt_match);
	256	if (!np) {
	257	pr_err("Can't find DGT DT node\n");
	258	return;
	259	}
	260
	261	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
	262	percpu_offset = 0;
	263
	264	if (of_address_to_resource(np, 0, &res)) {
	265	pr_err("Failed to parse DGT resource\n");
	266	return;
	267	}
	268
	269	source_base = ioremap(res.start + percpu_offset, resource_size(&res));
	270	if (!source_base) {
	271	pr_err("Failed to map source base\n");
	272	return;
	273	}
	274
	275	if (!of_address_to_resource(np, 1, &res)) {
	276	dgt_clk_ctl = ioremap(res.start + percpu_offset,
	277	resource_size(&res));
	278	if (!dgt_clk_ctl) {
	279	pr_err("Failed to map DGT control base\n");
	280	return;
	281	}
	282	writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
	283	iounmap(dgt_clk_ctl);
	284	}
	285
	286	if (of_property_read_u32(np, "clock-frequency", &freq)) {
	287	pr_err("Unknown frequency\n");
	288	return;
	289	}
	290	of_node_put(np);
	291
292	msm_timer_init(freq, 32, irq, !!percpu_offset);
293	}
6e332163 SB	294	#endif
6e332163 SB	295
4312a7ef SB	296	static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
	297	{
	298	event_base = ioremap(event, SZ_64);
	299	if (!event_base) {
	300	pr_err("Failed to map event base\n");
	301	return 1;
	302	}
	303	source_base = ioremap(source, SZ_64);
	304	if (!source_base) {
	305	pr_err("Failed to map source base\n");
	306	return 1;
	307	}
	308	return 0;
	309	}
	310
6bb27d73	311	void __init msm7x01_timer_init(void)
4312a7ef SB	312	{
	313	struct clocksource *cs = &msm_clocksource;
	314
	315	if (msm_timer_map(0xc0100000, 0xc0100010))
	316	return;
	317	cs->read = msm_read_timer_count_shift;
	318	cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
	319	/* 600 KHz */
	320	msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
	321	false);
	322	}
	323
6bb27d73	324	void __init msm7x30_timer_init(void)
4312a7ef SB	325	{
	326	if (msm_timer_map(0xc0100004, 0xc0100024))
	327	return;
	328	msm_timer_init(24576000 / 4, 32, 1, false);
	329	}
	330
6bb27d73	331	void __init qsd8x50_timer_init(void)
4312a7ef SB	332	{
	333	if (msm_timer_map(0xAC100000, 0xAC100010))
	334	return;
	335	msm_timer_init(19200000 / 4, 32, 7, false);
	336	}