[deliverable/linux.git] / arch / arm / mach-mv78xx0 / common.c

/*
 * arch/arm/mach-mv78xx0/common.c
 *
 * Core functions for Marvell MV78xx0 SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/ata_platform.h>
#include <linux/clk-provider.h>
#include <linux/ethtool.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include <plat/addr-map.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * Common bits
 ****************************************************************************/
int mv78xx0_core_index(void)
{
	u32 extra;

	/*
	 * Read Extra Features register.
	 */
	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));

	return !!(extra & 0x00004000);
}

static int get_hclk(void)
{
	int hclk;

	/*
	 * HCLK tick rate is configured by DEV_D[7:5] pins.
	 */
	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
	case 0:
		hclk = 166666667;
		break;
	case 1:
		hclk = 200000000;
		break;
	case 2:
		hclk = 266666667;
		break;
	case 3:
		hclk = 333333333;
		break;
	case 4:
		hclk = 400000000;
		break;
	default:
		panic("unknown HCLK PLL setting: %.8x\n",
			readl(SAMPLE_AT_RESET_LOW));
	}

	return hclk;
}

static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
{
	u32 cfg;

	/*
	 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
	 * PCLK/L2CLK by bits [19:14].
	 */
	if (core_index == 0) {
		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
	} else {
		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
	}

	/*
	 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
	 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
	 */
	*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;

	/*
	 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
	 * ratio (1, 2, 3).
	 */
	*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
}

static int get_tclk(void)
{
	int tclk_freq;

	/*
	 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
	 */
	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
	case 1:
		tclk_freq = 166666667;
		break;
	case 3:
		tclk_freq = 200000000;
		break;
	default:
		panic("unknown TCLK PLL setting: %.8x\n",
			readl(SAMPLE_AT_RESET_HIGH));
	}

	return tclk_freq;
}


/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc mv78xx0_io_desc[] __initdata = {
	{
		.virtual	= MV78XX0_CORE_REGS_VIRT_BASE,
		.pfn		= 0,
		.length		= MV78XX0_CORE_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= MV78XX0_PCIE_IO_VIRT_BASE(0),
		.pfn		= __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
		.length		= MV78XX0_PCIE_IO_SIZE * 8,
		.type		= MT_DEVICE,
	}, {
		.virtual	= MV78XX0_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
		.length		= MV78XX0_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init mv78xx0_map_io(void)
{
	unsigned long phys;

	/*
	 * Map the right set of per-core registers depending on
	 * which core we are running on.
	 */
	if (mv78xx0_core_index() == 0) {
		phys = MV78XX0_CORE0_REGS_PHYS_BASE;
	} else {
		phys = MV78XX0_CORE1_REGS_PHYS_BASE;
	}
	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);

	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
}


/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static struct clk *tclk;

static void __init clk_init(void)
{
	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
				       get_tclk());

	orion_clkdev_init(tclk);
}

/*****************************************************************************
 * EHCI
 ****************************************************************************/
void __init mv78xx0_ehci0_init(void)
{
	orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init mv78xx0_ehci1_init(void)
{
	orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}


/*****************************************************************************
 * EHCI2
 ****************************************************************************/
void __init mv78xx0_ehci2_init(void)
{
	orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}


/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data,
			GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
			IRQ_MV78XX0_GE_ERR,
			MV643XX_TX_CSUM_DEFAULT_LIMIT);
}


/*****************************************************************************
 * GE01
 ****************************************************************************/
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge01_init(eth_data,
			GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
			NO_IRQ,
			MV643XX_TX_CSUM_DEFAULT_LIMIT);
}


/*****************************************************************************
 * GE10
 ****************************************************************************/
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
{
	u32 dev, rev;

	/*
	 * On the Z0, ge10 and ge11 are internally connected back
	 * to back, and not brought out.
	 */
	mv78xx0_pcie_id(&dev, &rev);
	if (dev == MV78X00_Z0_DEV_ID) {
		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
		eth_data->speed = SPEED_1000;
		eth_data->duplex = DUPLEX_FULL;
	}

	orion_ge10_init(eth_data,
			GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
			NO_IRQ);
}


/*****************************************************************************
 * GE11
 ****************************************************************************/
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
{
	u32 dev, rev;

	/*
	 * On the Z0, ge10 and ge11 are internally connected back
	 * to back, and not brought out.
	 */
	mv78xx0_pcie_id(&dev, &rev);
	if (dev == MV78X00_Z0_DEV_ID) {
		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
		eth_data->speed = SPEED_1000;
		eth_data->duplex = DUPLEX_FULL;
	}

	orion_ge11_init(eth_data,
			GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
			NO_IRQ);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init mv78xx0_i2c_init(void)
{
	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init mv78xx0_uart0_init(void)
{
	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
			 IRQ_MV78XX0_UART_0, tclk);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init mv78xx0_uart1_init(void)
{
	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
			 IRQ_MV78XX0_UART_1, tclk);
}


/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init mv78xx0_uart2_init(void)
{
	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
			 IRQ_MV78XX0_UART_2, tclk);
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init mv78xx0_uart3_init(void)
{
	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
			 IRQ_MV78XX0_UART_3, tclk);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init mv78xx0_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static void mv78xx0_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_MV78XX0_TIMER_1, get_tclk());
}

struct sys_timer mv78xx0_timer = {
	.init = mv78xx0_timer_init,
};


/*****************************************************************************
 * General
 ****************************************************************************/
static char * __init mv78xx0_id(void)
{
	u32 dev, rev;

	mv78xx0_pcie_id(&dev, &rev);

	if (dev == MV78X00_Z0_DEV_ID) {
		if (rev == MV78X00_REV_Z0)
			return "MV78X00-Z0";
		else
			return "MV78X00-Rev-Unsupported";
	} else if (dev == MV78100_DEV_ID) {
		if (rev == MV78100_REV_A0)
			return "MV78100-A0";
		else if (rev == MV78100_REV_A1)
			return "MV78100-A1";
		else
			return "MV78100-Rev-Unsupported";
	} else if (dev == MV78200_DEV_ID) {
		if (rev == MV78100_REV_A0)
			return "MV78200-A0";
		else
			return "MV78200-Rev-Unsupported";
	} else {
		return "Device-Unknown";
	}
}

static int __init is_l2_writethrough(void)
{
	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
}

void __init mv78xx0_init(void)
{
	int core_index;
	int hclk;
	int pclk;
	int l2clk;

	core_index = mv78xx0_core_index();
	hclk = get_hclk();
	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);

	printk(KERN_INFO "%s ", mv78xx0_id());
	printk("core #%d, ", core_index);
	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
	printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);

	mv78xx0_setup_cpu_mbus();

#ifdef CONFIG_CACHE_FEROCEON_L2
	feroceon_l2_init(is_l2_writethrough());
#endif

	/* Setup root of clk tree */
	clk_init();
}

void mv78xx0_restart(char mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
794d15b2 SS	1	/*
	2	* arch/arm/mach-mv78xx0/common.c
	3	*
	4	* Core functions for Marvell MV78xx0 SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/serial_8250.h>
794d15b2	15	#include <linux/ata_platform.h>
2f129bf4	16	#include <linux/clk-provider.h>
712424fd	17	#include <linux/ethtool.h>
794d15b2 SS	18	#include <asm/mach/map.h>
794d15b2 SS	19	#include <asm/mach/time.h>
a09e64fb	20	#include <mach/mv78xx0.h>
fdd8b079	21	#include <mach/bridge-regs.h>
6f088f1d	22	#include <plat/cache-feroceon-l2.h>
72053353	23	#include <plat/ehci-orion.h>
6f088f1d LB	24	#include <plat/orion_nand.h>
6f088f1d LB	25	#include <plat/time.h>
28a2b450	26	#include <plat/common.h>
45173d5e	27	#include <plat/addr-map.h>
794d15b2 SS	28	#include "common.h"
794d15b2 SS	29
28a2b450	30	static int get_tclk(void);
794d15b2 SS	31
	32	/*****************************************************************************
	33	* Common bits
	34	****************************************************************************/
	35	int mv78xx0_core_index(void)
	36	{
	37	u32 extra;
	38
	39	/*
	40	* Read Extra Features register.
	41	*/
	42	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
	43
	44	return !!(extra & 0x00004000);
	45	}
	46
	47	static int get_hclk(void)
	48	{
	49	int hclk;
	50
	51	/*
	52	* HCLK tick rate is configured by DEV_D[7:5] pins.
	53	*/
	54	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
	55	case 0:
	56	hclk = 166666667;
	57	break;
	58	case 1:
	59	hclk = 200000000;
	60	break;
	61	case 2:
	62	hclk = 266666667;
	63	break;
	64	case 3:
	65	hclk = 333333333;
	66	break;
	67	case 4:
	68	hclk = 400000000;
	69	break;
	70	default:
	71	panic("unknown HCLK PLL setting: %.8x\n",
	72	readl(SAMPLE_AT_RESET_LOW));
	73	}
	74
	75	return hclk;
	76	}
	77
	78	static void get_pclk_l2clk(int hclk, int core_index, int pclk, int l2clk)
	79	{
	80	u32 cfg;
	81
	82	/*
	83	* Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
	84	* PCLK/L2CLK by bits [19:14].
	85	*/
	86	if (core_index == 0) {
	87	cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
	88	} else {
	89	cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
	90	}
	91
	92	/*
	93	* Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
	94	* ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
95	*/
96	pclk = ((u64)hclk (2 + (cfg & 0xf))) >> 1;
97
98	/*
99	* Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
100	* ratio (1, 2, 3).
101	*/
102	l2clk = pclk / (((cfg >> 4) & 3) + 1);
103	}
104
105	static int get_tclk(void)
106	{
2f129bf4	107	int tclk_freq;
794d15b2 SS	108
	109	/*
	110	* TCLK tick rate is configured by DEV_A[2:0] strap pins.
	111	*/
	112	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
	113	case 1:
2f129bf4	114	tclk_freq = 166666667;
794d15b2 SS	115	break;
794d15b2 SS	116	case 3:
2f129bf4	117	tclk_freq = 200000000;
794d15b2 SS	118	break;
	119	default:
	120	panic("unknown TCLK PLL setting: %.8x\n",
	121	readl(SAMPLE_AT_RESET_HIGH));
	122	}
	123
2f129bf4	124	return tclk_freq;
794d15b2 SS	125	}
	126
	127
	128	/*****************************************************************************
	129	* I/O Address Mapping
	130	****************************************************************************/
	131	static struct map_desc mv78xx0_io_desc[] __initdata = {
	132	{
	133	.virtual = MV78XX0_CORE_REGS_VIRT_BASE,
	134	.pfn = 0,
	135	.length = MV78XX0_CORE_REGS_SIZE,
	136	.type = MT_DEVICE,
	137	}, {
	138	.virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
	139	.pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
	140	.length = MV78XX0_PCIE_IO_SIZE * 8,
	141	.type = MT_DEVICE,
	142	}, {
	143	.virtual = MV78XX0_REGS_VIRT_BASE,
	144	.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
	145	.length = MV78XX0_REGS_SIZE,
	146	.type = MT_DEVICE,
	147	},
	148	};
	149
	150	void __init mv78xx0_map_io(void)
	151	{
	152	unsigned long phys;
	153
	154	/*
	155	* Map the right set of per-core registers depending on
	156	* which core we are running on.
	157	*/
	158	if (mv78xx0_core_index() == 0) {
	159	phys = MV78XX0_CORE0_REGS_PHYS_BASE;
	160	} else {
	161	phys = MV78XX0_CORE1_REGS_PHYS_BASE;
	162	}
	163	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
	164
	165	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
	166	}
	167
	168
2f129bf4 AL	169	/*****************************************************************************
	170	* CLK tree
	171	****************************************************************************/
	172	static struct clk *tclk;
	173
	174	static void __init clk_init(void)
	175	{
	176	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
	177	get_tclk());
4574b886 AL	178
4574b886 AL	179	orion_clkdev_init(tclk);
2f129bf4 AL	180	}
2f129bf4 AL	181
794d15b2 SS	182	/*****************************************************************************
	183	* EHCI
	184	****************************************************************************/
794d15b2 SS	185	void __init mv78xx0_ehci0_init(void)
794d15b2 SS	186	{
72053353	187	orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
794d15b2 SS	188	}
	189
	190
	191	/*****************************************************************************
	192	* EHCI1
	193	****************************************************************************/
794d15b2 SS	194	void __init mv78xx0_ehci1_init(void)
794d15b2 SS	195	{
db33f4de	196	orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
794d15b2 SS	197	}
	198
	199
	200	/*****************************************************************************
	201	* EHCI2
	202	****************************************************************************/
794d15b2 SS	203	void __init mv78xx0_ehci2_init(void)
794d15b2 SS	204	{
db33f4de	205	orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
794d15b2 SS	206	}
	207
	208
	209	/*****************************************************************************
	210	* GE00
	211	****************************************************************************/
794d15b2 SS	212	void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	213	{
db33f4de	214	orion_ge00_init(eth_data,
7e3819d8	215	GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
58569aee APR	216	IRQ_MV78XX0_GE_ERR,
58569aee APR	217	MV643XX_TX_CSUM_DEFAULT_LIMIT);
794d15b2 SS	218	}
	219
	220
	221	/*****************************************************************************
	222	* GE01
	223	****************************************************************************/
794d15b2 SS	224	void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	225	{
db33f4de	226	orion_ge01_init(eth_data,
7e3819d8	227	GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
58569aee APR	228	NO_IRQ,
58569aee APR	229	MV643XX_TX_CSUM_DEFAULT_LIMIT);
794d15b2 SS	230	}
	231
	232
	233	/*****************************************************************************
	234	* GE10
	235	****************************************************************************/
794d15b2 SS	236	void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	237	{
712424fd LB	238	u32 dev, rev;
712424fd LB	239
712424fd LB	240	/*
	241	* On the Z0, ge10 and ge11 are internally connected back
	242	* to back, and not brought out.
	243	*/
	244	mv78xx0_pcie_id(&dev, &rev);
	245	if (dev == MV78X00_Z0_DEV_ID) {
	246	eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
	247	eth_data->speed = SPEED_1000;
	248	eth_data->duplex = DUPLEX_FULL;
	249	}
	250
db33f4de	251	orion_ge10_init(eth_data,
7e3819d8	252	GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
452503eb	253	NO_IRQ);
794d15b2 SS	254	}
	255
	256
	257	/*****************************************************************************
	258	* GE11
	259	****************************************************************************/
794d15b2 SS	260	void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	261	{
712424fd LB	262	u32 dev, rev;
712424fd LB	263
712424fd LB	264	/*
	265	* On the Z0, ge10 and ge11 are internally connected back
	266	* to back, and not brought out.
	267	*/
	268	mv78xx0_pcie_id(&dev, &rev);
	269	if (dev == MV78X00_Z0_DEV_ID) {
	270	eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
	271	eth_data->speed = SPEED_1000;
	272	eth_data->duplex = DUPLEX_FULL;
	273	}
	274
db33f4de	275	orion_ge11_init(eth_data,
7e3819d8	276	GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
452503eb	277	NO_IRQ);
794d15b2 SS	278	}
794d15b2 SS	279
69359943	280	/*****************************************************************************
aac7ffa3	281	* I2C
69359943	282	****************************************************************************/
69359943 RV	283	void __init mv78xx0_i2c_init(void)
69359943 RV	284	{
aac7ffa3 AL	285	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
aac7ffa3 AL	286	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
69359943	287	}
794d15b2 SS	288
	289	/*****************************************************************************
	290	* SATA
	291	****************************************************************************/
794d15b2 SS	292	void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
794d15b2 SS	293	{
db33f4de	294	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
794d15b2 SS	295	}
	296
	297
	298	/*****************************************************************************
	299	* UART0
	300	****************************************************************************/
794d15b2 SS	301	void __init mv78xx0_uart0_init(void)
794d15b2 SS	302	{
28a2b450	303	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
74c33576	304	IRQ_MV78XX0_UART_0, tclk);
794d15b2 SS	305	}
	306
	307
	308	/*****************************************************************************
	309	* UART1
	310	****************************************************************************/
794d15b2 SS	311	void __init mv78xx0_uart1_init(void)
794d15b2 SS	312	{
28a2b450	313	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
74c33576	314	IRQ_MV78XX0_UART_1, tclk);
794d15b2 SS	315	}
	316
	317
	318	/*****************************************************************************
	319	* UART2
	320	****************************************************************************/
794d15b2 SS	321	void __init mv78xx0_uart2_init(void)
794d15b2 SS	322	{
28a2b450	323	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
74c33576	324	IRQ_MV78XX0_UART_2, tclk);
794d15b2 SS	325	}
794d15b2 SS	326
794d15b2 SS	327	/*****************************************************************************
	328	* UART3
	329	****************************************************************************/
794d15b2 SS	330	void __init mv78xx0_uart3_init(void)
794d15b2 SS	331	{
28a2b450	332	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
74c33576	333	IRQ_MV78XX0_UART_3, tclk);
794d15b2 SS	334	}
794d15b2 SS	335
794d15b2 SS	336	/*****************************************************************************
	337	* Time handling
	338	****************************************************************************/
4ee1f6b5 LB	339	void __init mv78xx0_init_early(void)
	340	{
	341	orion_time_set_base(TIMER_VIRT_BASE);
	342	}
	343
794d15b2 SS	344	static void mv78xx0_timer_init(void)
794d15b2 SS	345	{
4ee1f6b5 LB	346	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	347	IRQ_MV78XX0_TIMER_1, get_tclk());
794d15b2 SS	348	}
	349
	350	struct sys_timer mv78xx0_timer = {
	351	.init = mv78xx0_timer_init,
	352	};
	353
	354
	355	/*****************************************************************************
	356	* General
	357	****************************************************************************/
cfdeb637 LB	358	static char * __init mv78xx0_id(void)
	359	{
	360	u32 dev, rev;
	361
	362	mv78xx0_pcie_id(&dev, &rev);
	363
	364	if (dev == MV78X00_Z0_DEV_ID) {
	365	if (rev == MV78X00_REV_Z0)
	366	return "MV78X00-Z0";
	367	else
	368	return "MV78X00-Rev-Unsupported";
	369	} else if (dev == MV78100_DEV_ID) {
	370	if (rev == MV78100_REV_A0)
	371	return "MV78100-A0";
662aeced LB	372	else if (rev == MV78100_REV_A1)
662aeced LB	373	return "MV78100-A1";
cfdeb637 LB	374	else
	375	return "MV78100-Rev-Unsupported";
	376	} else if (dev == MV78200_DEV_ID) {
	377	if (rev == MV78100_REV_A0)
	378	return "MV78200-A0";
	379	else
	380	return "MV78200-Rev-Unsupported";
	381	} else {
	382	return "Device-Unknown";
	383	}
	384	}
	385
794d15b2 SS	386	static int __init is_l2_writethrough(void)
	387	{
	388	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
	389	}
	390
	391	void __init mv78xx0_init(void)
	392	{
	393	int core_index;
	394	int hclk;
	395	int pclk;
	396	int l2clk;
794d15b2 SS	397
	398	core_index = mv78xx0_core_index();
	399	hclk = get_hclk();
	400	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
794d15b2	401
cfdeb637 LB	402	printk(KERN_INFO "%s ", mv78xx0_id());
cfdeb637 LB	403	printk("core #%d, ", core_index);
794d15b2 SS	404	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
	405	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
	406	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
2f129bf4	407	printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
794d15b2 SS	408
	409	mv78xx0_setup_cpu_mbus();
	410
	411	#ifdef CONFIG_CACHE_FEROCEON_L2
	412	feroceon_l2_init(is_l2_writethrough());
	413	#endif
2f129bf4 AL	414
	415	/* Setup root of clk tree */
	416	clk_init();
794d15b2	417	}
9635f9cd RK	418
	419	void mv78xx0_restart(char mode, const char *cmd)
	420	{
	421	/*
	422	* Enable soft reset to assert RSTOUTn.
	423	*/
	424	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	425
	426	/*
	427	* Assert soft reset.
	428	*/
	429	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	430
	431	while (1)
	432	;
	433	}