[deliverable/linux.git] / arch / arm / mach-mv78xx0 / common.c

/*
 * arch/arm/mach-mv78xx0/common.c
 *
 * Core functions for Marvell MV78xx0 SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/ata_platform.h>
#include <linux/clk-provider.h>
#include <linux/ethtool.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <linux/platform_data/mtd-orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include <plat/addr-map.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * Common bits
 ****************************************************************************/
int mv78xx0_core_index(void)
{
	u32 extra;

	/*
	 * Read Extra Features register.
	 */
	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));

	return !!(extra & 0x00004000);
}

static int get_hclk(void)
{
	int hclk;

	/*
	 * HCLK tick rate is configured by DEV_D[7:5] pins.
	 */
	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
	case 0:
		hclk = 166666667;
		break;
	case 1:
		hclk = 200000000;
		break;
	case 2:
		hclk = 266666667;
		break;
	case 3:
		hclk = 333333333;
		break;
	case 4:
		hclk = 400000000;
		break;
	default:
		panic("unknown HCLK PLL setting: %.8x\n",
			readl(SAMPLE_AT_RESET_LOW));
	}

	return hclk;
}

static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
{
	u32 cfg;

	/*
	 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
	 * PCLK/L2CLK by bits [19:14].
	 */
	if (core_index == 0) {
		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
	} else {
		cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
	}

	/*
	 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
	 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
	 */
	*pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;

	/*
	 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
	 * ratio (1, 2, 3).
	 */
	*l2clk = *pclk / (((cfg >> 4) & 3) + 1);
}

static int get_tclk(void)
{
	int tclk_freq;

	/*
	 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
	 */
	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
	case 1:
		tclk_freq = 166666667;
		break;
	case 3:
		tclk_freq = 200000000;
		break;
	default:
		panic("unknown TCLK PLL setting: %.8x\n",
			readl(SAMPLE_AT_RESET_HIGH));
	}

	return tclk_freq;
}


/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc mv78xx0_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
		.pfn		= 0,
		.length		= MV78XX0_CORE_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long) MV78XX0_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
		.length		= MV78XX0_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init mv78xx0_map_io(void)
{
	unsigned long phys;

	/*
	 * Map the right set of per-core registers depending on
	 * which core we are running on.
	 */
	if (mv78xx0_core_index() == 0) {
		phys = MV78XX0_CORE0_REGS_PHYS_BASE;
	} else {
		phys = MV78XX0_CORE1_REGS_PHYS_BASE;
	}
	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);

	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
}


/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static struct clk *tclk;

static void __init clk_init(void)
{
	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
				       get_tclk());

	orion_clkdev_init(tclk);
}

/*****************************************************************************
 * EHCI
 ****************************************************************************/
void __init mv78xx0_ehci0_init(void)
{
	orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init mv78xx0_ehci1_init(void)
{
	orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}


/*****************************************************************************
 * EHCI2
 ****************************************************************************/
void __init mv78xx0_ehci2_init(void)
{
	orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}


/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data,
			GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
			IRQ_MV78XX0_GE_ERR,
			MV643XX_TX_CSUM_DEFAULT_LIMIT);
}


/*****************************************************************************
 * GE01
 ****************************************************************************/
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge01_init(eth_data,
			GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
			NO_IRQ,
			MV643XX_TX_CSUM_DEFAULT_LIMIT);
}


/*****************************************************************************
 * GE10
 ****************************************************************************/
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
{
	u32 dev, rev;

	/*
	 * On the Z0, ge10 and ge11 are internally connected back
	 * to back, and not brought out.
	 */
	mv78xx0_pcie_id(&dev, &rev);
	if (dev == MV78X00_Z0_DEV_ID) {
		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
		eth_data->speed = SPEED_1000;
		eth_data->duplex = DUPLEX_FULL;
	}

	orion_ge10_init(eth_data,
			GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
			NO_IRQ);
}


/*****************************************************************************
 * GE11
 ****************************************************************************/
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
{
	u32 dev, rev;

	/*
	 * On the Z0, ge10 and ge11 are internally connected back
	 * to back, and not brought out.
	 */
	mv78xx0_pcie_id(&dev, &rev);
	if (dev == MV78X00_Z0_DEV_ID) {
		eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
		eth_data->speed = SPEED_1000;
		eth_data->duplex = DUPLEX_FULL;
	}

	orion_ge11_init(eth_data,
			GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
			NO_IRQ);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init mv78xx0_i2c_init(void)
{
	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init mv78xx0_uart0_init(void)
{
	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
			 IRQ_MV78XX0_UART_0, tclk);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init mv78xx0_uart1_init(void)
{
	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
			 IRQ_MV78XX0_UART_1, tclk);
}


/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init mv78xx0_uart2_init(void)
{
	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
			 IRQ_MV78XX0_UART_2, tclk);
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init mv78xx0_uart3_init(void)
{
	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
			 IRQ_MV78XX0_UART_3, tclk);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init mv78xx0_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
	if (mv78xx0_core_index() == 0)
		mvebu_mbus_init("marvell,mv78xx0-mbus",
				BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
				DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
	else
		mvebu_mbus_init("marvell,mv78xx0-mbus",
				BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
				DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
}

void __init_refok mv78xx0_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_MV78XX0_TIMER_1, get_tclk());
}


/*****************************************************************************
 * General
 ****************************************************************************/
static char * __init mv78xx0_id(void)
{
	u32 dev, rev;

	mv78xx0_pcie_id(&dev, &rev);

	if (dev == MV78X00_Z0_DEV_ID) {
		if (rev == MV78X00_REV_Z0)
			return "MV78X00-Z0";
		else
			return "MV78X00-Rev-Unsupported";
	} else if (dev == MV78100_DEV_ID) {
		if (rev == MV78100_REV_A0)
			return "MV78100-A0";
		else if (rev == MV78100_REV_A1)
			return "MV78100-A1";
		else
			return "MV78100-Rev-Unsupported";
	} else if (dev == MV78200_DEV_ID) {
		if (rev == MV78100_REV_A0)
			return "MV78200-A0";
		else
			return "MV78200-Rev-Unsupported";
	} else {
		return "Device-Unknown";
	}
}

static int __init is_l2_writethrough(void)
{
	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
}

void __init mv78xx0_init(void)
{
	int core_index;
	int hclk;
	int pclk;
	int l2clk;

	core_index = mv78xx0_core_index();
	hclk = get_hclk();
	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);

	printk(KERN_INFO "%s ", mv78xx0_id());
	printk("core #%d, ", core_index);
	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
	printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);

#ifdef CONFIG_CACHE_FEROCEON_L2
	feroceon_l2_init(is_l2_writethrough());
#endif

	/* Setup root of clk tree */
	clk_init();
}

void mv78xx0_restart(char mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
794d15b2 SS	1	/*
	2	* arch/arm/mach-mv78xx0/common.c
	3	*
	4	* Core functions for Marvell MV78xx0 SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/serial_8250.h>
794d15b2	15	#include <linux/ata_platform.h>
2f129bf4	16	#include <linux/clk-provider.h>
712424fd	17	#include <linux/ethtool.h>
794d15b2 SS	18	#include <asm/mach/map.h>
794d15b2 SS	19	#include <asm/mach/time.h>
a09e64fb	20	#include <mach/mv78xx0.h>
fdd8b079	21	#include <mach/bridge-regs.h>
6f088f1d	22	#include <plat/cache-feroceon-l2.h>
c02cecb9 AB	23	#include <linux/platform_data/usb-ehci-orion.h>
c02cecb9 AB	24	#include <linux/platform_data/mtd-orion_nand.h>
6f088f1d	25	#include <plat/time.h>
28a2b450	26	#include <plat/common.h>
45173d5e	27	#include <plat/addr-map.h>
794d15b2 SS	28	#include "common.h"
794d15b2 SS	29
28a2b450	30	static int get_tclk(void);
794d15b2 SS	31
	32	/*****************************************************************************
	33	* Common bits
	34	****************************************************************************/
	35	int mv78xx0_core_index(void)
	36	{
	37	u32 extra;
	38
	39	/*
	40	* Read Extra Features register.
	41	*/
	42	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
	43
	44	return !!(extra & 0x00004000);
	45	}
	46
	47	static int get_hclk(void)
	48	{
	49	int hclk;
	50
	51	/*
	52	* HCLK tick rate is configured by DEV_D[7:5] pins.
	53	*/
	54	switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
	55	case 0:
	56	hclk = 166666667;
	57	break;
	58	case 1:
	59	hclk = 200000000;
	60	break;
	61	case 2:
	62	hclk = 266666667;
	63	break;
	64	case 3:
	65	hclk = 333333333;
	66	break;
	67	case 4:
	68	hclk = 400000000;
	69	break;
	70	default:
	71	panic("unknown HCLK PLL setting: %.8x\n",
	72	readl(SAMPLE_AT_RESET_LOW));
	73	}
	74
	75	return hclk;
	76	}
	77
	78	static void get_pclk_l2clk(int hclk, int core_index, int pclk, int l2clk)
	79	{
	80	u32 cfg;
	81
	82	/*
	83	* Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
	84	* PCLK/L2CLK by bits [19:14].
	85	*/
	86	if (core_index == 0) {
	87	cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
	88	} else {
	89	cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
	90	}
	91
	92	/*
	93	* Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
	94	* ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
95	*/
96	pclk = ((u64)hclk (2 + (cfg & 0xf))) >> 1;
97
98	/*
99	* Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
100	* ratio (1, 2, 3).
101	*/
102	l2clk = pclk / (((cfg >> 4) & 3) + 1);
103	}
104
105	static int get_tclk(void)
106	{
2f129bf4	107	int tclk_freq;
794d15b2 SS	108
	109	/*
	110	* TCLK tick rate is configured by DEV_A[2:0] strap pins.
	111	*/
	112	switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
	113	case 1:
2f129bf4	114	tclk_freq = 166666667;
794d15b2 SS	115	break;
794d15b2 SS	116	case 3:
2f129bf4	117	tclk_freq = 200000000;
794d15b2 SS	118	break;
	119	default:
	120	panic("unknown TCLK PLL setting: %.8x\n",
	121	readl(SAMPLE_AT_RESET_HIGH));
	122	}
	123
2f129bf4	124	return tclk_freq;
794d15b2 SS	125	}
	126
	127
	128	/*****************************************************************************
	129	* I/O Address Mapping
	130	****************************************************************************/
	131	static struct map_desc mv78xx0_io_desc[] __initdata = {
	132	{
383b9961	133	.virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
794d15b2 SS	134	.pfn = 0,
	135	.length = MV78XX0_CORE_REGS_SIZE,
	136	.type = MT_DEVICE,
794d15b2	137	}, {
383b9961	138	.virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
794d15b2 SS	139	.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
	140	.length = MV78XX0_REGS_SIZE,
	141	.type = MT_DEVICE,
	142	},
	143	};
	144
	145	void __init mv78xx0_map_io(void)
	146	{
	147	unsigned long phys;
	148
	149	/*
	150	* Map the right set of per-core registers depending on
	151	* which core we are running on.
	152	*/
	153	if (mv78xx0_core_index() == 0) {
	154	phys = MV78XX0_CORE0_REGS_PHYS_BASE;
	155	} else {
	156	phys = MV78XX0_CORE1_REGS_PHYS_BASE;
	157	}
	158	mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
	159
	160	iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
	161	}
	162
	163
2f129bf4 AL	164	/*****************************************************************************
	165	* CLK tree
	166	****************************************************************************/
	167	static struct clk *tclk;
	168
	169	static void __init clk_init(void)
	170	{
	171	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
	172	get_tclk());
4574b886 AL	173
4574b886 AL	174	orion_clkdev_init(tclk);
2f129bf4 AL	175	}
2f129bf4 AL	176
794d15b2 SS	177	/*****************************************************************************
	178	* EHCI
	179	****************************************************************************/
794d15b2 SS	180	void __init mv78xx0_ehci0_init(void)
794d15b2 SS	181	{
72053353	182	orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
794d15b2 SS	183	}
	184
	185
	186	/*****************************************************************************
	187	* EHCI1
	188	****************************************************************************/
794d15b2 SS	189	void __init mv78xx0_ehci1_init(void)
794d15b2 SS	190	{
db33f4de	191	orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
794d15b2 SS	192	}
	193
	194
	195	/*****************************************************************************
	196	* EHCI2
	197	****************************************************************************/
794d15b2 SS	198	void __init mv78xx0_ehci2_init(void)
794d15b2 SS	199	{
db33f4de	200	orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
794d15b2 SS	201	}
	202
	203
	204	/*****************************************************************************
	205	* GE00
	206	****************************************************************************/
794d15b2 SS	207	void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	208	{
db33f4de	209	orion_ge00_init(eth_data,
7e3819d8	210	GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
58569aee APR	211	IRQ_MV78XX0_GE_ERR,
58569aee APR	212	MV643XX_TX_CSUM_DEFAULT_LIMIT);
794d15b2 SS	213	}
	214
	215
	216	/*****************************************************************************
	217	* GE01
	218	****************************************************************************/
794d15b2 SS	219	void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	220	{
db33f4de	221	orion_ge01_init(eth_data,
7e3819d8	222	GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
58569aee APR	223	NO_IRQ,
58569aee APR	224	MV643XX_TX_CSUM_DEFAULT_LIMIT);
794d15b2 SS	225	}
	226
	227
	228	/*****************************************************************************
	229	* GE10
	230	****************************************************************************/
794d15b2 SS	231	void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	232	{
712424fd LB	233	u32 dev, rev;
712424fd LB	234
712424fd LB	235	/*
	236	* On the Z0, ge10 and ge11 are internally connected back
	237	* to back, and not brought out.
	238	*/
	239	mv78xx0_pcie_id(&dev, &rev);
	240	if (dev == MV78X00_Z0_DEV_ID) {
	241	eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
	242	eth_data->speed = SPEED_1000;
	243	eth_data->duplex = DUPLEX_FULL;
	244	}
	245
db33f4de	246	orion_ge10_init(eth_data,
7e3819d8	247	GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
452503eb	248	NO_IRQ);
794d15b2 SS	249	}
	250
	251
	252	/*****************************************************************************
	253	* GE11
	254	****************************************************************************/
794d15b2 SS	255	void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
794d15b2 SS	256	{
712424fd LB	257	u32 dev, rev;
712424fd LB	258
712424fd LB	259	/*
	260	* On the Z0, ge10 and ge11 are internally connected back
	261	* to back, and not brought out.
	262	*/
	263	mv78xx0_pcie_id(&dev, &rev);
	264	if (dev == MV78X00_Z0_DEV_ID) {
	265	eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
	266	eth_data->speed = SPEED_1000;
	267	eth_data->duplex = DUPLEX_FULL;
	268	}
	269
db33f4de	270	orion_ge11_init(eth_data,
7e3819d8	271	GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
452503eb	272	NO_IRQ);
794d15b2 SS	273	}
794d15b2 SS	274
69359943	275	/*****************************************************************************
aac7ffa3	276	* I2C
69359943	277	****************************************************************************/
69359943 RV	278	void __init mv78xx0_i2c_init(void)
69359943 RV	279	{
aac7ffa3 AL	280	orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
aac7ffa3 AL	281	orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
69359943	282	}
794d15b2 SS	283
	284	/*****************************************************************************
	285	* SATA
	286	****************************************************************************/
794d15b2 SS	287	void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
794d15b2 SS	288	{
db33f4de	289	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
794d15b2 SS	290	}
	291
	292
	293	/*****************************************************************************
	294	* UART0
	295	****************************************************************************/
794d15b2 SS	296	void __init mv78xx0_uart0_init(void)
794d15b2 SS	297	{
28a2b450	298	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
74c33576	299	IRQ_MV78XX0_UART_0, tclk);
794d15b2 SS	300	}
	301
	302
	303	/*****************************************************************************
	304	* UART1
	305	****************************************************************************/
794d15b2 SS	306	void __init mv78xx0_uart1_init(void)
794d15b2 SS	307	{
28a2b450	308	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
74c33576	309	IRQ_MV78XX0_UART_1, tclk);
794d15b2 SS	310	}
	311
	312
	313	/*****************************************************************************
	314	* UART2
	315	****************************************************************************/
794d15b2 SS	316	void __init mv78xx0_uart2_init(void)
794d15b2 SS	317	{
28a2b450	318	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
74c33576	319	IRQ_MV78XX0_UART_2, tclk);
794d15b2 SS	320	}
794d15b2 SS	321
794d15b2 SS	322	/*****************************************************************************
	323	* UART3
	324	****************************************************************************/
794d15b2 SS	325	void __init mv78xx0_uart3_init(void)
794d15b2 SS	326	{
28a2b450	327	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
74c33576	328	IRQ_MV78XX0_UART_3, tclk);
794d15b2 SS	329	}
794d15b2 SS	330
794d15b2 SS	331	/*****************************************************************************
	332	* Time handling
	333	****************************************************************************/
4ee1f6b5 LB	334	void __init mv78xx0_init_early(void)
	335	{
	336	orion_time_set_base(TIMER_VIRT_BASE);
95b80e0a TP	337	if (mv78xx0_core_index() == 0)
	338	mvebu_mbus_init("marvell,mv78xx0-mbus",
	339	BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
	340	DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
	341	else
	342	mvebu_mbus_init("marvell,mv78xx0-mbus",
	343	BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
	344	DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
4ee1f6b5 LB	345	}
4ee1f6b5 LB	346
6bb27d73	347	void __init_refok mv78xx0_timer_init(void)
794d15b2	348	{
4ee1f6b5 LB	349	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	350	IRQ_MV78XX0_TIMER_1, get_tclk());
794d15b2 SS	351	}
794d15b2 SS	352
794d15b2 SS	353
	354	/*****************************************************************************
	355	* General
	356	****************************************************************************/
cfdeb637 LB	357	static char * __init mv78xx0_id(void)
	358	{
	359	u32 dev, rev;
	360
	361	mv78xx0_pcie_id(&dev, &rev);
	362
	363	if (dev == MV78X00_Z0_DEV_ID) {
	364	if (rev == MV78X00_REV_Z0)
	365	return "MV78X00-Z0";
	366	else
	367	return "MV78X00-Rev-Unsupported";
	368	} else if (dev == MV78100_DEV_ID) {
	369	if (rev == MV78100_REV_A0)
	370	return "MV78100-A0";
662aeced LB	371	else if (rev == MV78100_REV_A1)
662aeced LB	372	return "MV78100-A1";
cfdeb637 LB	373	else
	374	return "MV78100-Rev-Unsupported";
	375	} else if (dev == MV78200_DEV_ID) {
	376	if (rev == MV78100_REV_A0)
	377	return "MV78200-A0";
	378	else
	379	return "MV78200-Rev-Unsupported";
	380	} else {
	381	return "Device-Unknown";
	382	}
	383	}
	384
794d15b2 SS	385	static int __init is_l2_writethrough(void)
	386	{
	387	return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
	388	}
	389
	390	void __init mv78xx0_init(void)
	391	{
	392	int core_index;
	393	int hclk;
	394	int pclk;
	395	int l2clk;
794d15b2 SS	396
	397	core_index = mv78xx0_core_index();
	398	hclk = get_hclk();
	399	get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
794d15b2	400
cfdeb637 LB	401	printk(KERN_INFO "%s ", mv78xx0_id());
cfdeb637 LB	402	printk("core #%d, ", core_index);
794d15b2 SS	403	printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
	404	printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
	405	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
2f129bf4	406	printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
794d15b2	407
794d15b2 SS	408	#ifdef CONFIG_CACHE_FEROCEON_L2
	409	feroceon_l2_init(is_l2_writethrough());
	410	#endif
2f129bf4 AL	411
	412	/* Setup root of clk tree */
	413	clk_init();
794d15b2	414	}
9635f9cd RK	415
	416	void mv78xx0_restart(char mode, const char *cmd)
	417	{
	418	/*
	419	* Enable soft reset to assert RSTOUTn.
	420	*/
	421	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	422
	423	/*
	424	* Assert soft reset.
	425	*/
	426	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	427
	428	while (1)
	429	;
	430	}