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fdd8b079 NP |
1 | /* |
2 | * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. This program is licensed "as is" without any | |
6 | * warranty of any kind, whether express or implied. | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | |
10 | #define __ASM_ARCH_BRIDGE_REGS_H | |
11 | ||
12 | #include <mach/mv78xx0.h> | |
13 | ||
14 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | |
15 | #define L2_WRITETHROUGH 0x00020000 | |
16 | ||
17 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | |
18 | #define SOFT_RESET_OUT_EN 0x00000004 | |
19 | ||
20 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | |
21 | #define SOFT_RESET 0x00000001 | |
22 | ||
fdd8b079 NP |
23 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
24 | ||
25 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | |
26 | #define IRQ_CAUSE_ERR_OFF 0x0000 | |
27 | #define IRQ_CAUSE_LOW_OFF 0x0004 | |
28 | #define IRQ_CAUSE_HIGH_OFF 0x0008 | |
29 | #define IRQ_MASK_ERR_OFF 0x000c | |
30 | #define IRQ_MASK_LOW_OFF 0x0010 | |
31 | #define IRQ_MASK_HIGH_OFF 0x0014 | |
32 | ||
33 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | |
1e0c1ce0 | 34 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) |
fdd8b079 NP |
35 | |
36 | #endif |