ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU

[deliverable/linux.git] / arch / arm / mach-mvebu / Kconfig

config ARCH_MVEBU
	bool "Marvell Engineering Business Unit (MVEBU) SoCs" if ARCH_MULTI_V7
	select ARCH_SUPPORTS_BIG_ENDIAN
	select CLKSRC_MMIO
	select COMMON_CLK
	select GENERIC_CLOCKEVENTS
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select PINCTRL
	select PLAT_ORION
	select SPARSE_IRQ
	select CLKDEV_LOOKUP
	select MVEBU_MBUS
	select ZONE_DMA if ARM_LPAE
	select ARCH_REQUIRE_GPIOLIB
	select MIGHT_HAVE_PCI
	select PCI_QUIRKS if PCI

if ARCH_MVEBU

menu "Marvell EBU SoC variants"

config MACH_ARMADA_370_XP
	bool
	select ARMADA_370_XP_TIMER
	select HAVE_SMP
	select CACHE_L2X0
	select CPU_PJ4B

config MACH_ARMADA_370
	bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
	select ARMADA_370_CLK
	select MACH_ARMADA_370_XP
	select PINCTRL_ARMADA_370
	help
	  Say 'Y' here if you want your kernel to support boards based
	  on the Marvell Armada 370 SoC with device tree.

config MACH_ARMADA_XP
	bool "Marvell Armada XP boards" if ARCH_MULTI_V7
	select ARMADA_XP_CLK
	select MACH_ARMADA_370_XP
	select PINCTRL_ARMADA_XP
	help
	  Say 'Y' here if you want your kernel to support boards based
	  on the Marvell Armada XP SoC with device tree.

endmenu

endif