[deliverable/linux.git] / arch / arm / mach-mvebu / board-v7.c

/*
 * Device Tree support for Armada 370 and XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <linux/signal.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/smp_scu.h>
#include "armada-370-xp.h"
#include "common.h"
#include "coherency.h"
#include "mvebu-soc-id.h"

/*
 * Enables the SCU when available. Obviously, this is only useful on
 * Cortex-A based SOCs, not on PJ4B based ones.
 */
static void __init mvebu_scu_enable(void)
{
	void __iomem *scu_base;

	struct device_node *np =
		of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
	if (np) {
		scu_base = of_iomap(np, 0);
		scu_enable(scu_base);
		of_node_put(np);
	}
}

/*
 * Early versions of Armada 375 SoC have a bug where the BootROM
 * leaves an external data abort pending. The kernel is hit by this
 * data abort as soon as it enters userspace, because it unmasks the
 * data aborts at this moment. We register a custom abort handler
 * below to ignore the first data abort to work around this
 * problem.
 */
static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
					struct pt_regs *regs)
{
	static int ignore_first;

	if (!ignore_first && fsr == 0x1406) {
		ignore_first = 1;
		return 0;
	}

	return 1;
}

static void __init mvebu_init_irq(void)
{
	irqchip_init();
	mvebu_scu_enable();
	coherency_init();
	BUG_ON(mvebu_mbus_dt_init(coherency_available()));
}

static void __init external_abort_quirk(void)
{
	u32 dev, rev;

	if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
		return;

	hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
			"imprecise external abort");
}

static void __init i2c_quirk(void)
{
	struct device_node *np;
	u32 dev, rev;

	/*
	 * Only revisons more recent than A0 support the offload
	 * mechanism. We can exit only if we are sure that we can
	 * get the SoC revision and it is more recent than A0.
	 */
	if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
		return;

	for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
		struct property *new_compat;

		new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);

		new_compat->name = kstrdup("compatible", GFP_KERNEL);
		new_compat->length = sizeof("marvell,mv78230-a0-i2c");
		new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
						GFP_KERNEL);

		of_update_property(np, new_compat);
	}
	return;
}

#define A375_Z1_THERMAL_FIXUP_OFFSET 0xc

static void __init thermal_quirk(void)
{
	struct device_node *np;
	u32 dev, rev;
	int res;

	/*
	 * The early SoC Z1 revision needs a quirk to be applied in order
	 * for the thermal controller to work properly. This quirk breaks
	 * the thermal support if applied on a SoC that doesn't need it,
	 * so we enforce the SoC revision to be known.
	 */
	res = mvebu_get_soc_id(&dev, &rev);
	if (res < 0 || (res == 0 && rev > ARMADA_375_Z1_REV))
		return;

	for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
		struct property *prop;
		__be32 newval, *newprop, *oldprop;
		int len;

		/*
		 * The register offset is at a wrong location. This quirk
		 * creates a new reg property as a clone of the previous
		 * one and corrects the offset.
		 */
		oldprop = (__be32 *)of_get_property(np, "reg", &len);
		if (!oldprop)
			continue;

		/* Create a duplicate of the 'reg' property */
		prop = kzalloc(sizeof(*prop), GFP_KERNEL);
		prop->length = len;
		prop->name = kstrdup("reg", GFP_KERNEL);
		prop->value = kzalloc(len, GFP_KERNEL);
		memcpy(prop->value, oldprop, len);

		/* Fixup the register offset of the second entry */
		oldprop += 2;
		newprop = (__be32 *)prop->value + 2;
		newval = cpu_to_be32(be32_to_cpu(*oldprop) -
				     A375_Z1_THERMAL_FIXUP_OFFSET);
		*newprop = newval;
		of_update_property(np, prop);

		/*
		 * The thermal controller needs some quirk too, so let's change
		 * the compatible string to reflect this and allow the driver
		 * the take the necessary action.
		 */
		prop = kzalloc(sizeof(*prop), GFP_KERNEL);
		prop->name = kstrdup("compatible", GFP_KERNEL);
		prop->length = sizeof("marvell,armada375-z1-thermal");
		prop->value = kstrdup("marvell,armada375-z1-thermal",
						GFP_KERNEL);
		of_update_property(np, prop);
	}
	return;
}

static void __init mvebu_dt_init(void)
{
	if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
		i2c_quirk();
	if (of_machine_is_compatible("marvell,a375-db")) {
		external_abort_quirk();
		thermal_quirk();
	}

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char * const armada_370_xp_dt_compat[] = {
	"marvell,armada-370-xp",
	NULL,
};

DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
	.l2c_aux_val	= 0,
	.l2c_aux_mask	= ~0,
	.smp		= smp_ops(armada_xp_smp_ops),
	.init_machine	= mvebu_dt_init,
	.init_irq       = mvebu_init_irq,
	.restart	= mvebu_restart,
	.dt_compat	= armada_370_xp_dt_compat,
MACHINE_END

static const char * const armada_375_dt_compat[] = {
	"marvell,armada375",
	NULL,
};

DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
	.l2c_aux_val	= 0,
	.l2c_aux_mask	= ~0,
	.init_irq       = mvebu_init_irq,
	.init_machine	= mvebu_dt_init,
	.restart	= mvebu_restart,
	.dt_compat	= armada_375_dt_compat,
MACHINE_END

static const char * const armada_38x_dt_compat[] = {
	"marvell,armada380",
	"marvell,armada385",
	NULL,
};

DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
	.l2c_aux_val	= 0,
	.l2c_aux_mask	= ~0,
	.init_irq       = mvebu_init_irq,
	.restart	= mvebu_restart,
	.dt_compat	= armada_38x_dt_compat,
MACHINE_END
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Device Tree support for Armada 370 and XP platforms.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
9cbbc515	17	#include <linux/clk-provider.h>
d834d26a	18	#include <linux/of_address.h>
9ae6f740 TP	19	#include <linux/of_platform.h>
9ae6f740 TP	20	#include <linux/io.h>
573145f0	21	#include <linux/clocksource.h>
53d2f889	22	#include <linux/dma-mapping.h>
87e1bed4	23	#include <linux/mbus.h>
9e128041	24	#include <linux/signal.h>
85e618a1	25	#include <linux/slab.h>
01178890	26	#include <linux/irqchip.h>
e33369cb	27	#include <asm/hardware/cache-l2x0.h>
9ae6f740 TP	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/time.h>
8e6ac203	31	#include <asm/smp_scu.h>
6eb5be34	32	#include "armada-370-xp.h"
9ae6f740	33	#include "common.h"
45f5984a	34	#include "coherency.h"
85e618a1	35	#include "mvebu-soc-id.h"
9ae6f740	36
8e6ac203 TP	37	/*
	38	* Enables the SCU when available. Obviously, this is only useful on
	39	* Cortex-A based SOCs, not on PJ4B based ones.
	40	*/
	41	static void __init mvebu_scu_enable(void)
	42	{
	43	void __iomem *scu_base;
	44
	45	struct device_node *np =
	46	of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
	47	if (np) {
	48	scu_base = of_iomap(np, 0);
	49	scu_enable(scu_base);
	50	of_node_put(np);
	51	}
	52	}
	53
ca4a6f87 TP	54	/*
	55	* Early versions of Armada 375 SoC have a bug where the BootROM
	56	* leaves an external data abort pending. The kernel is hit by this
	57	* data abort as soon as it enters userspace, because it unmasks the
	58	* data aborts at this moment. We register a custom abort handler
	59	* below to ignore the first data abort to work around this
	60	* problem.
	61	*/
	62	static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
	63	struct pt_regs *regs)
	64	{
	65	static int ignore_first;
	66
	67	if (!ignore_first && fsr == 0x1406) {
	68	ignore_first = 1;
	69	return 0;
	70	}
	71
	72	return 1;
	73	}
	74
01178890	75	static void __init mvebu_init_irq(void)
d834d26a	76	{
01178890	77	irqchip_init();
8e6ac203	78	mvebu_scu_enable();
d834d26a	79	coherency_init();
5686a1e5	80	BUG_ON(mvebu_mbus_dt_init(coherency_available()));
752ef800 TP	81	}
	82
	83	static void __init external_abort_quirk(void)
	84	{
	85	u32 dev, rev;
ca4a6f87	86
752ef800 TP	87	if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
	88	return;
	89
	90	hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
	91	"imprecise external abort");
53d2f889 GC	92	}
53d2f889 GC	93
85e618a1 GC	94	static void __init i2c_quirk(void)
	95	{
	96	struct device_node *np;
	97	u32 dev, rev;
	98
	99	/*
	100	* Only revisons more recent than A0 support the offload
	101	* mechanism. We can exit only if we are sure that we can
	102	* get the SoC revision and it is more recent than A0.
	103	*/
8eee0f81	104	if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
85e618a1 GC	105	return;
	106
	107	for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
	108	struct property *new_compat;
	109
	110	new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
	111
	112	new_compat->name = kstrdup("compatible", GFP_KERNEL);
	113	new_compat->length = sizeof("marvell,mv78230-a0-i2c");
	114	new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
	115	GFP_KERNEL);
	116
	117	of_update_property(np, new_compat);
	118	}
	119	return;
	120	}
	121
5fd62066 EG	122	#define A375_Z1_THERMAL_FIXUP_OFFSET 0xc
	123
	124	static void __init thermal_quirk(void)
	125	{
	126	struct device_node *np;
	127	u32 dev, rev;
9d637348	128	int res;
5fd62066	129
9d637348 EG	130	/*
	131	* The early SoC Z1 revision needs a quirk to be applied in order
	132	* for the thermal controller to work properly. This quirk breaks
	133	* the thermal support if applied on a SoC that doesn't need it,
	134	* so we enforce the SoC revision to be known.
	135	*/
	136	res = mvebu_get_soc_id(&dev, &rev);
	137	if (res < 0 \|\| (res == 0 && rev > ARMADA_375_Z1_REV))
5fd62066 EG	138	return;
	139
	140	for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
	141	struct property *prop;
	142	__be32 newval, newprop, oldprop;
	143	int len;
	144
	145	/*
	146	* The register offset is at a wrong location. This quirk
	147	* creates a new reg property as a clone of the previous
	148	* one and corrects the offset.
	149	*/
	150	oldprop = (__be32 *)of_get_property(np, "reg", &len);
	151	if (!oldprop)
	152	continue;
	153
	154	/* Create a duplicate of the 'reg' property */
	155	prop = kzalloc(sizeof(*prop), GFP_KERNEL);
	156	prop->length = len;
	157	prop->name = kstrdup("reg", GFP_KERNEL);
	158	prop->value = kzalloc(len, GFP_KERNEL);
	159	memcpy(prop->value, oldprop, len);
	160
	161	/* Fixup the register offset of the second entry */
	162	oldprop += 2;
	163	newprop = (__be32 *)prop->value + 2;
	164	newval = cpu_to_be32(be32_to_cpu(*oldprop) -
	165	A375_Z1_THERMAL_FIXUP_OFFSET);
	166	*newprop = newval;
	167	of_update_property(np, prop);
	168
	169	/*
	170	* The thermal controller needs some quirk too, so let's change
9d637348 EG	171	* the compatible string to reflect this and allow the driver
9d637348 EG	172	* the take the necessary action.
5fd62066 EG	173	*/
	174	prop = kzalloc(sizeof(*prop), GFP_KERNEL);
	175	prop->name = kstrdup("compatible", GFP_KERNEL);
	176	prop->length = sizeof("marvell,armada375-z1-thermal");
	177	prop->value = kstrdup("marvell,armada375-z1-thermal",
	178	GFP_KERNEL);
	179	of_update_property(np, prop);
	180	}
	181	return;
	182	}
	183
99b3d294	184	static void __init mvebu_dt_init(void)
9ae6f740	185	{
85e618a1 GC	186	if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
85e618a1 GC	187	i2c_quirk();
752ef800 TP	188	if (of_machine_is_compatible("marvell,a375-db")) {
752ef800 TP	189	external_abort_quirk();
5fd62066	190	thermal_quirk();
752ef800	191	}
5fd62066	192
9ae6f740 TP	193	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	194	}
	195
61505e11 TP	196	static const char * const armada_370_xp_dt_compat[] = {
61505e11 TP	197	"marvell,armada-370-xp",
9ae6f740 TP	198	NULL,
	199	};
	200
a017dbb6	201	DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
9847cf04 RK	202	.l2c_aux_val = 0,
9847cf04 RK	203	.l2c_aux_mask = ~0,
45f5984a	204	.smp = smp_ops(armada_xp_smp_ops),
99b3d294	205	.init_machine = mvebu_dt_init,
01178890	206	.init_irq = mvebu_init_irq,
9ae6f740	207	.restart = mvebu_restart,
61505e11	208	.dt_compat = armada_370_xp_dt_compat,
9ae6f740	209	MACHINE_END
d3ce7f25 GC	210
	211	static const char * const armada_375_dt_compat[] = {
	212	"marvell,armada375",
	213	NULL,
	214	};
	215
	216	DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
9847cf04 RK	217	.l2c_aux_val = 0,
9847cf04 RK	218	.l2c_aux_mask = ~0,
01178890	219	.init_irq = mvebu_init_irq,
5fd62066	220	.init_machine = mvebu_dt_init,
d3ce7f25 GC	221	.restart = mvebu_restart,
	222	.dt_compat = armada_375_dt_compat,
	223	MACHINE_END
9aa30f1c TP	224
	225	static const char * const armada_38x_dt_compat[] = {
	226	"marvell,armada380",
	227	"marvell,armada385",
	228	NULL,
	229	};
	230
	231	DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
9847cf04 RK	232	.l2c_aux_val = 0,
9847cf04 RK	233	.l2c_aux_mask = ~0,
01178890	234	.init_irq = mvebu_init_irq,
9aa30f1c TP	235	.restart = mvebu_restart,
	236	.dt_compat = armada_38x_dt_compat,
	237	MACHINE_END