[deliverable/linux.git] / arch / arm / mach-mvebu / coherency.c

/*
 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
 * platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
 * responsible for ensuring hardware coherency between all CPUs and between
 * CPUs and I/O masters. This file initializes the coherency fabric and
 * supplies basic routines for configuring and controlling hardware coherency
 */

#define pr_fmt(fmt) "mvebu-coherency: " fmt

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <linux/pci.h>
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#include <asm/dma-mapping.h>
#include "coherency.h"
#include "mvebu-soc-id.h"

unsigned long coherency_phys_base;
void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;

/* Coherency fabric registers */
#define IO_SYNC_BARRIER_CTL_OFFSET		   0x0

enum {
	COHERENCY_FABRIC_TYPE_NONE,
	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
	COHERENCY_FABRIC_TYPE_ARMADA_375,
	COHERENCY_FABRIC_TYPE_ARMADA_380,
};

static const struct of_device_id of_coherency_table[] = {
	{.compatible = "marvell,coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
	{.compatible = "marvell,armada-375-coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
	{.compatible = "marvell,armada-380-coherency-fabric",
	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
	{ /* end of list */ },
};

/* Functions defined in coherency_ll.S */
int ll_enable_coherency(void);
void ll_add_cpu_to_smp_group(void);

int set_cpu_coherent(void)
{
	if (!coherency_base) {
		pr_warn("Can't make current CPU cache coherent.\n");
		pr_warn("Coherency fabric is not initialized\n");
		return 1;
	}

	ll_add_cpu_to_smp_group();
	return ll_enable_coherency();
}

static int mvebu_hwcc_notifier(struct notifier_block *nb,
			       unsigned long event, void *__dev)
{
	struct device *dev = __dev;

	if (event != BUS_NOTIFY_ADD_DEVICE)
		return NOTIFY_DONE;
	set_dma_ops(dev, &arm_coherent_dma_ops);

	return NOTIFY_OK;
}

static struct notifier_block mvebu_hwcc_nb = {
	.notifier_call = mvebu_hwcc_notifier,
};

static struct notifier_block mvebu_hwcc_pci_nb = {
	.notifier_call = mvebu_hwcc_notifier,
};

static void __init armada_370_coherency_init(struct device_node *np)
{
	struct resource res;

	of_address_to_resource(np, 0, &res);
	coherency_phys_base = res.start;
	/*
	 * Ensure secondary CPUs will see the updated value,
	 * which they read before they join the coherency
	 * fabric, and therefore before they are coherent with
	 * the boot CPU cache.
	 */
	sync_cache_w(&coherency_phys_base);
	coherency_base = of_iomap(np, 0);
	coherency_cpu_base = of_iomap(np, 1);
	set_cpu_coherent();
}

/*
 * This ioremap hook is used on Armada 375/38x to ensure that PCIe
 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
 * is needed as a workaround for a deadlock issue between the PCIe
 * interface and the cache controller.
 */
static void __iomem *
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
			      unsigned int mtype, void *caller)
{
	struct resource pcie_mem;

	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);

	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
		mtype = MT_UNCACHED;

	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}

static void __init armada_375_380_coherency_init(struct device_node *np)
{
	struct device_node *cache_dn;

	coherency_cpu_base = of_iomap(np, 0);
	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;

	/*
	 * We should switch the PL310 to I/O coherency mode only if
	 * I/O coherency is actually enabled.
	 */
	if (!coherency_available())
		return;

	/*
	 * Add the PL310 property "arm,io-coherent". This makes sure the
	 * outer sync operation is not used, which allows to
	 * workaround the system erratum that causes deadlocks when
	 * doing PCIe in an SMP situation on Armada 375 and Armada
	 * 38x.
	 */
	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
		struct property *p;

		p = kzalloc(sizeof(*p), GFP_KERNEL);
		p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
		of_add_property(cache_dn, p);
	}
}

static int coherency_type(void)
{
	struct device_node *np;
	const struct of_device_id *match;
	int type;

	/*
	 * The coherency fabric is needed:
	 * - For coherency between processors on Armada XP, so only
	 *   when SMP is enabled.
	 * - For coherency between the processor and I/O devices, but
	 *   this coherency requires many pre-requisites (write
	 *   allocate cache policy, shareable pages, SMP bit set) that
	 *   are only meant in SMP situations.
	 *
	 * Note that this means that on Armada 370, there is currently
	 * no way to use hardware I/O coherency, because even when
	 * CONFIG_SMP is enabled, is_smp() returns false due to the
	 * Armada 370 being a single-core processor. To lift this
	 * limitation, we would have to find a way to make the cache
	 * policy set to write-allocate (on all Armada SoCs), and to
	 * set the shareable attribute in page tables (on all Armada
	 * SoCs except the Armada 370). Unfortunately, such decisions
	 * are taken very early in the kernel boot process, at a point
	 * where we don't know yet on which SoC we are running.

	 */
	if (!is_smp())
		return COHERENCY_FABRIC_TYPE_NONE;

	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
	if (!np)
		return COHERENCY_FABRIC_TYPE_NONE;

	type = (int) match->data;

	of_node_put(np);

	return type;
}

int coherency_available(void)
{
	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
}

int __init coherency_init(void)
{
	int type = coherency_type();
	struct device_node *np;

	np = of_find_matching_node(NULL, of_coherency_table);

	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
		armada_370_coherency_init(np);
	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
		 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
		armada_375_380_coherency_init(np);

	of_node_put(np);

	return 0;
}

static int __init coherency_late_init(void)
{
	if (coherency_available())
		bus_register_notifier(&platform_bus_type,
				      &mvebu_hwcc_nb);
	return 0;
}

postcore_initcall(coherency_late_init);

#if IS_ENABLED(CONFIG_PCI)
static int __init coherency_pci_init(void)
{
	if (coherency_available())
		bus_register_notifier(&pci_bus_type,
				       &mvebu_hwcc_pci_nb);
	return 0;
}

arch_initcall(coherency_pci_init);
#endif
Commit	Line	Data
009f1315	1	/*
e12f12ac TP	2	* Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
e12f12ac TP	3	* platforms.
009f1315 GC	4	*
	5	* Copyright (C) 2012 Marvell
	6	*
	7	* Yehuda Yitschak <yehuday@marvell.com>
	8	* Gregory Clement <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*
e12f12ac	15	* The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
009f1315 GC	16	* responsible for ensuring hardware coherency between all CPUs and between
	17	* CPUs and I/O masters. This file initializes the coherency fabric and
	18	* supplies basic routines for configuring and controlling hardware coherency
	19	*/
	20
5ab5afd8 TP	21	#define pr_fmt(fmt) "mvebu-coherency: " fmt
5ab5afd8 TP	22
009f1315 GC	23	#include <linux/kernel.h>
	24	#include <linux/init.h>
	25	#include <linux/of_address.h>
	26	#include <linux/io.h>
	27	#include <linux/smp.h>
e60304f8 GC	28	#include <linux/dma-mapping.h>
e60304f8 GC	29	#include <linux/platform_device.h>
5ab5afd8 TP	30	#include <linux/slab.h>
5ab5afd8 TP	31	#include <linux/mbus.h>
b0063aad	32	#include <linux/pci.h>
009f1315	33	#include <asm/smp_plat.h>
580ff0ee	34	#include <asm/cacheflush.h>
497a9230	35	#include <asm/mach/map.h>
1bd4d8a6	36	#include <asm/dma-mapping.h>
b12634e3	37	#include "coherency.h"
39438567	38	#include "mvebu-soc-id.h"
009f1315	39
8bd26e3a	40	unsigned long coherency_phys_base;
ccd6a131	41	void __iomem *coherency_base;
e60304f8	42	static void __iomem *coherency_cpu_base;
009f1315 GC	43
009f1315 GC	44	/* Coherency fabric registers */
e60304f8 GC	45	#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
e60304f8 GC	46
924d38f4	47	enum {
501f928e	48	COHERENCY_FABRIC_TYPE_NONE,
924d38f4	49	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
77fa4b9a	50	COHERENCY_FABRIC_TYPE_ARMADA_375,
d0de9323	51	COHERENCY_FABRIC_TYPE_ARMADA_380,
924d38f4 TP	52	};
924d38f4 TP	53
444d2d33	54	static const struct of_device_id of_coherency_table[] = {
924d38f4 TP	55	{.compatible = "marvell,coherency-fabric",
924d38f4 TP	56	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
77fa4b9a TP	57	{.compatible = "marvell,armada-375-coherency-fabric",
77fa4b9a TP	58	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
d0de9323 TP	59	{.compatible = "marvell,armada-380-coherency-fabric",
d0de9323 TP	60	.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
009f1315 GC	61	{ /* end of list */ },
	62	};
	63
2e8a5942 GC	64	/* Functions defined in coherency_ll.S */
	65	int ll_enable_coherency(void);
	66	void ll_add_cpu_to_smp_group(void);
009f1315	67
952f4ca7	68	int set_cpu_coherent(void)
009f1315 GC	69	{
009f1315 GC	70	if (!coherency_base) {
b41375f7	71	pr_warn("Can't make current CPU cache coherent.\n");
009f1315 GC	72	pr_warn("Coherency fabric is not initialized\n");
	73	return 1;
	74	}
	75
2e8a5942 GC	76	ll_add_cpu_to_smp_group();
2e8a5942 GC	77	return ll_enable_coherency();
009f1315 GC	78	}
009f1315 GC	79
b0063aad TP	80	static int mvebu_hwcc_notifier(struct notifier_block *nb,
b0063aad TP	81	unsigned long event, void *__dev)
e60304f8 GC	82	{
	83	struct device *dev = __dev;
	84
	85	if (event != BUS_NOTIFY_ADD_DEVICE)
	86	return NOTIFY_DONE;
1bd4d8a6	87	set_dma_ops(dev, &arm_coherent_dma_ops);
e60304f8 GC	88
	89	return NOTIFY_OK;
	90	}
	91
b0063aad TP	92	static struct notifier_block mvebu_hwcc_nb = {
b0063aad TP	93	.notifier_call = mvebu_hwcc_notifier,
e60304f8 GC	94	};
e60304f8 GC	95
a728b977 EG	96	static struct notifier_block mvebu_hwcc_pci_nb = {
	97	.notifier_call = mvebu_hwcc_notifier,
	98	};
	99
924d38f4 TP	100	static void __init armada_370_coherency_init(struct device_node *np)
	101	{
	102	struct resource res;
	103
	104	of_address_to_resource(np, 0, &res);
	105	coherency_phys_base = res.start;
	106	/*
	107	* Ensure secondary CPUs will see the updated value,
	108	* which they read before they join the coherency
	109	* fabric, and therefore before they are coherent with
	110	* the boot CPU cache.
	111	*/
	112	sync_cache_w(&coherency_phys_base);
	113	coherency_base = of_iomap(np, 0);
	114	coherency_cpu_base = of_iomap(np, 1);
952f4ca7	115	set_cpu_coherent();
924d38f4 TP	116	}
924d38f4 TP	117
497a9230 TP	118	/*
	119	* This ioremap hook is used on Armada 375/38x to ensure that PCIe
	120	* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
	121	* is needed as a workaround for a deadlock issue between the PCIe
	122	* interface and the cache controller.
	123	*/
	124	static void __iomem *
	125	armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
	126	unsigned int mtype, void *caller)
	127	{
	128	struct resource pcie_mem;
	129
	130	mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
	131
	132	if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
	133	mtype = MT_UNCACHED;
	134
	135	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
	136	}
	137
d0de9323	138	static void __init armada_375_380_coherency_init(struct device_node *np)
77fa4b9a	139	{
497a9230 TP	140	struct device_node *cache_dn;
497a9230 TP	141
77fa4b9a	142	coherency_cpu_base = of_iomap(np, 0);
497a9230 TP	143	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
497a9230 TP	144
dcad6887 TP	145	/*
	146	* We should switch the PL310 to I/O coherency mode only if
	147	* I/O coherency is actually enabled.
	148	*/
	149	if (!coherency_available())
	150	return;
	151
497a9230 TP	152	/*
	153	* Add the PL310 property "arm,io-coherent". This makes sure the
	154	* outer sync operation is not used, which allows to
	155	* workaround the system erratum that causes deadlocks when
	156	* doing PCIe in an SMP situation on Armada 375 and Armada
	157	* 38x.
	158	*/
	159	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
	160	struct property *p;
	161
	162	p = kzalloc(sizeof(*p), GFP_KERNEL);
	163	p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
	164	of_add_property(cache_dn, p);
	165	}
77fa4b9a TP	166	}
77fa4b9a TP	167
501f928e	168	static int coherency_type(void)
009f1315 GC	169	{
009f1315 GC	170	struct device_node *np;
5fbba080	171	const struct of_device_id *match;
e5535545	172	int type;
009f1315	173
e5535545 TP	174	/*
	175	* The coherency fabric is needed:
	176	* - For coherency between processors on Armada XP, so only
	177	* when SMP is enabled.
	178	* - For coherency between the processor and I/O devices, but
	179	* this coherency requires many pre-requisites (write
	180	* allocate cache policy, shareable pages, SMP bit set) that
	181	* are only meant in SMP situations.
	182	*
	183	* Note that this means that on Armada 370, there is currently
	184	* no way to use hardware I/O coherency, because even when
	185	* CONFIG_SMP is enabled, is_smp() returns false due to the
	186	* Armada 370 being a single-core processor. To lift this
	187	* limitation, we would have to find a way to make the cache
	188	* policy set to write-allocate (on all Armada SoCs), and to
	189	* set the shareable attribute in page tables (on all Armada
	190	* SoCs except the Armada 370). Unfortunately, such decisions
	191	* are taken very early in the kernel boot process, at a point
	192	* where we don't know yet on which SoC we are running.
	193
	194	*/
	195	if (!is_smp())
	196	return COHERENCY_FABRIC_TYPE_NONE;
924d38f4	197
e5535545 TP	198	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
	199	if (!np)
	200	return COHERENCY_FABRIC_TYPE_NONE;
924d38f4	201
e5535545	202	type = (int) match->data;
77fa4b9a	203
e5535545	204	of_node_put(np);
009f1315	205
e5535545	206	return type;
009f1315	207	}
865e0527	208
501f928e	209	int coherency_available(void)
865e0527	210	{
1bd4d8a6	211	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
501f928e TP	212	}
	213
	214	int __init coherency_init(void)
	215	{
	216	int type = coherency_type();
abe511ac JZ	217	struct device_node *np;
	218
	219	np = of_find_matching_node(NULL, of_coherency_table);
501f928e TP	220
	221	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
	222	armada_370_coherency_init(np);
d0de9323 TP	223	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 \|\|
	224	type == COHERENCY_FABRIC_TYPE_ARMADA_380)
	225	armada_375_380_coherency_init(np);
501f928e	226
2eb04ae0 TP	227	of_node_put(np);
2eb04ae0 TP	228
501f928e TP	229	return 0;
	230	}
	231
	232	static int __init coherency_late_init(void)
	233	{
ef01c6c3 TP	234	if (coherency_available())
	235	bus_register_notifier(&platform_bus_type,
	236	&mvebu_hwcc_nb);
865e0527 TP	237	return 0;
	238	}
	239
	240	postcore_initcall(coherency_late_init);
b0063aad	241
8828ccc3	242	#if IS_ENABLED(CONFIG_PCI)
b0063aad TP	243	static int __init coherency_pci_init(void)
	244	{
	245	if (coherency_available())
	246	bus_register_notifier(&pci_bus_type,
a728b977	247	&mvebu_hwcc_pci_nb);
b0063aad TP	248	return 0;
	249	}
	250
	251	arch_initcall(coherency_pci_init);
8828ccc3	252	#endif