[deliverable/linux.git] / arch / arm / mach-mvebu / platsmp.c

/*
 * Symmetric Multi Processing (SMP) support for Armada XP
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
 * This file implements the routines for preparing the SMP infrastructure
 * and waking up the secondary CPUs
 */

#include <linux/init.h>
#include <linux/smp.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/mbus.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "common.h"
#include "armada-370-xp.h"
#include "pmsu.h"
#include "coherency.h"

#define AXP_BOOTROM_BASE 0xfff00000
#define AXP_BOOTROM_SIZE 0x100000

static struct clk *__init get_cpu_clk(int cpu)
{
	struct clk *cpu_clk;
	struct device_node *np = of_get_cpu_node(cpu, NULL);

	if (WARN(!np, "missing cpu node\n"))
		return NULL;
	cpu_clk = of_clk_get(np, 0);
	if (WARN_ON(IS_ERR(cpu_clk)))
		return NULL;
	return cpu_clk;
}

static void __init set_secondary_cpus_clock(void)
{
	int thiscpu, cpu;
	unsigned long rate;
	struct clk *cpu_clk;

	thiscpu = smp_processor_id();
	cpu_clk = get_cpu_clk(thiscpu);
	if (!cpu_clk)
		return;
	clk_prepare_enable(cpu_clk);
	rate = clk_get_rate(cpu_clk);

	/* set all the other CPU clk to the same rate than the boot CPU */
	for_each_possible_cpu(cpu) {
		if (cpu == thiscpu)
			continue;
		cpu_clk = get_cpu_clk(cpu);
		if (!cpu_clk)
			return;
		clk_set_rate(cpu_clk, rate);
	}
}

static void armada_xp_secondary_init(unsigned int cpu)
{
	armada_xp_mpic_smp_cpu_init();
}

static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	pr_info("Booting CPU %d\n", cpu);

	armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);

	return 0;
}

static void __init armada_xp_smp_init_cpus(void)
{
	unsigned int ncores = num_possible_cpus();

	if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
		panic("Invalid number of CPUs in DT\n");

	set_smp_cross_call(armada_mpic_send_doorbell);
}

static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
{
	struct device_node *node;
	struct resource res;
	int err;

	set_secondary_cpus_clock();
	flush_cache_all();
	set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);

	/*
	 * In order to boot the secondary CPUs we need to ensure
	 * the bootROM is mapped at the correct address.
	 */
	node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
	if (!node)
		panic("Cannot find 'marvell,bootrom' compatible node");

	err = of_address_to_resource(node, 0, &res);
	if (err < 0)
		panic("Cannot get 'bootrom' node address");

	if (res.start != AXP_BOOTROM_BASE ||
	    resource_size(&res) != AXP_BOOTROM_SIZE)
		panic("The address for the BootROM is incorrect");
}

struct smp_operations armada_xp_smp_ops __initdata = {
	.smp_init_cpus		= armada_xp_smp_init_cpus,
	.smp_prepare_cpus	= armada_xp_smp_prepare_cpus,
	.smp_secondary_init	= armada_xp_secondary_init,
	.smp_boot_secondary	= armada_xp_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= armada_xp_cpu_die,
#endif
};
Commit	Line	Data
45f5984a GC	1	/*
	2	* Symmetric Multi Processing (SMP) support for Armada XP
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Yehuda Yitschak <yehuday@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*
	15	* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
	16	* This file implements the routines for preparing the SMP infrastructure
	17	* and waking up the secondary CPUs
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/smp.h>
	22	#include <linux/clk.h>
	23	#include <linux/of.h>
994c8c94	24	#include <linux/of_address.h>
87e1bed4	25	#include <linux/mbus.h>
45f5984a GC	26	#include <asm/cacheflush.h>
	27	#include <asm/smp_plat.h>
	28	#include "common.h"
	29	#include "armada-370-xp.h"
	30	#include "pmsu.h"
	31	#include "coherency.h"
	32
994c8c94 EG	33	#define AXP_BOOTROM_BASE 0xfff00000
	34	#define AXP_BOOTROM_SIZE 0x100000
	35
f6cec7cd SK	36	static struct clk *__init get_cpu_clk(int cpu)
	37	{
	38	struct clk *cpu_clk;
	39	struct device_node *np = of_get_cpu_node(cpu, NULL);
	40
	41	if (WARN(!np, "missing cpu node\n"))
	42	return NULL;
	43	cpu_clk = of_clk_get(np, 0);
	44	if (WARN_ON(IS_ERR(cpu_clk)))
	45	return NULL;
	46	return cpu_clk;
	47	}
	48
b12634e3	49	static void __init set_secondary_cpus_clock(void)
45f5984a	50	{
f6cec7cd	51	int thiscpu, cpu;
45f5984a	52	unsigned long rate;
f6cec7cd	53	struct clk *cpu_clk;
45f5984a GC	54
45f5984a GC	55	thiscpu = smp_processor_id();
f6cec7cd SK	56	cpu_clk = get_cpu_clk(thiscpu);
f6cec7cd SK	57	if (!cpu_clk)
45f5984a GC	58	return;
	59	clk_prepare_enable(cpu_clk);
	60	rate = clk_get_rate(cpu_clk);
	61
	62	/* set all the other CPU clk to the same rate than the boot CPU */
f6cec7cd SK	63	for_each_possible_cpu(cpu) {
	64	if (cpu == thiscpu)
	65	continue;
	66	cpu_clk = get_cpu_clk(cpu);
	67	if (!cpu_clk)
45f5984a	68	return;
f6cec7cd	69	clk_set_rate(cpu_clk, rate);
45f5984a GC	70	}
	71	}
	72
8bd26e3a	73	static void armada_xp_secondary_init(unsigned int cpu)
45f5984a GC	74	{
	75	armada_xp_mpic_smp_cpu_init();
	76	}
	77
8bd26e3a	78	static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
45f5984a GC	79	{
	80	pr_info("Booting CPU %d\n", cpu);
	81
	82	armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
	83
	84	return 0;
	85	}
	86
	87	static void __init armada_xp_smp_init_cpus(void)
	88	{
a7160b7e	89	unsigned int ncores = num_possible_cpus();
b21dcafe	90
b21dcafe TP	91	if (ncores == 0 \|\| ncores > ARMADA_XP_MAX_CPUS)
b21dcafe TP	92	panic("Invalid number of CPUs in DT\n");
45f5984a	93
45f5984a GC	94	set_smp_cross_call(armada_mpic_send_doorbell);
	95	}
	96
b12634e3	97	static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
45f5984a	98	{
994c8c94 EG	99	struct device_node *node;
	100	struct resource res;
	101	int err;
	102
45f5984a GC	103	set_secondary_cpus_clock();
	104	flush_cache_all();
	105	set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
994c8c94 EG	106
	107	/*
	108	* In order to boot the secondary CPUs we need to ensure
	109	* the bootROM is mapped at the correct address.
	110	*/
	111	node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
	112	if (!node)
	113	panic("Cannot find 'marvell,bootrom' compatible node");
	114
	115	err = of_address_to_resource(node, 0, &res);
	116	if (err < 0)
	117	panic("Cannot get 'bootrom' node address");
	118
	119	if (res.start != AXP_BOOTROM_BASE \|\|
	120	resource_size(&res) != AXP_BOOTROM_SIZE)
	121	panic("The address for the BootROM is incorrect");
45f5984a GC	122	}
	123
	124	struct smp_operations armada_xp_smp_ops __initdata = {
	125	.smp_init_cpus = armada_xp_smp_init_cpus,
	126	.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
	127	.smp_secondary_init = armada_xp_secondary_init,
	128	.smp_boot_secondary = armada_xp_boot_secondary,
	129	#ifdef CONFIG_HOTPLUG_CPU
	130	.cpu_die = armada_xp_cpu_die,
	131	#endif
	132	};