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7444dad2 GC |
1 | /* |
2 | * Power Management Service Unit(PMSU) support for Armada 370/XP platforms. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Yehuda Yitschak <yehuday@marvell.com> | |
7 | * Gregory Clement <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * The Armada 370 and Armada XP SOCs have a power management service | |
15 | * unit which is responsible for powering down and waking up CPUs and | |
16 | * other SOC units | |
17 | */ | |
18 | ||
bd045a1e TP |
19 | #define pr_fmt(fmt) "mvebu-pmsu: " fmt |
20 | ||
7444dad2 GC |
21 | #include <linux/kernel.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/smp.h> | |
49754ffe | 26 | #include <linux/resource.h> |
7444dad2 | 27 | #include <asm/smp_plat.h> |
49754ffe | 28 | #include "common.h" |
b12634e3 | 29 | #include "pmsu.h" |
7444dad2 GC |
30 | |
31 | static void __iomem *pmsu_mp_base; | |
7444dad2 | 32 | |
0c3acc74 GC |
33 | #define PMSU_BASE_OFFSET 0x100 |
34 | #define PMSU_REG_SIZE 0x1000 | |
35 | ||
36 | #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) | |
7444dad2 GC |
37 | |
38 | static struct of_device_id of_pmsu_table[] = { | |
0c3acc74 GC |
39 | { .compatible = "marvell,armada-370-pmsu", }, |
40 | { .compatible = "marvell,armada-370-xp-pmsu", }, | |
7444dad2 GC |
41 | { /* end of list */ }, |
42 | }; | |
43 | ||
44 | #ifdef CONFIG_SMP | |
45 | int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) | |
46 | { | |
49754ffe | 47 | int hw_cpu, ret; |
7444dad2 | 48 | |
49754ffe | 49 | if (!pmsu_mp_base) { |
7444dad2 | 50 | pr_warn("Can't boot CPU. PMSU is uninitialized\n"); |
49754ffe | 51 | return -ENODEV; |
7444dad2 GC |
52 | } |
53 | ||
54 | hw_cpu = cpu_logical_map(cpu_id); | |
55 | ||
56 | writel(virt_to_phys(boot_addr), pmsu_mp_base + | |
57 | PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); | |
58 | ||
49754ffe TP |
59 | ret = mvebu_cpu_reset_deassert(hw_cpu); |
60 | if (ret) { | |
61 | pr_warn("unable to boot CPU: %d\n", ret); | |
62 | return ret; | |
63 | } | |
7444dad2 GC |
64 | |
65 | return 0; | |
66 | } | |
67 | #endif | |
68 | ||
b12634e3 | 69 | static int __init armada_370_xp_pmsu_init(void) |
7444dad2 GC |
70 | { |
71 | struct device_node *np; | |
bd045a1e TP |
72 | struct resource res; |
73 | int ret = 0; | |
7444dad2 GC |
74 | |
75 | np = of_find_matching_node(NULL, of_pmsu_table); | |
bd045a1e TP |
76 | if (!np) |
77 | return 0; | |
78 | ||
79 | pr_info("Initializing Power Management Service Unit\n"); | |
80 | ||
81 | if (of_address_to_resource(np, 0, &res)) { | |
82 | pr_err("unable to get resource\n"); | |
83 | ret = -ENOENT; | |
84 | goto out; | |
7444dad2 GC |
85 | } |
86 | ||
0c3acc74 GC |
87 | if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) { |
88 | pr_warn(FW_WARN "deprecated pmsu binding\n"); | |
89 | res.start = res.start - PMSU_BASE_OFFSET; | |
90 | res.end = res.start + PMSU_REG_SIZE - 1; | |
91 | } | |
92 | ||
bd045a1e TP |
93 | if (!request_mem_region(res.start, resource_size(&res), |
94 | np->full_name)) { | |
95 | pr_err("unable to request region\n"); | |
96 | ret = -EBUSY; | |
97 | goto out; | |
98 | } | |
99 | ||
100 | pmsu_mp_base = ioremap(res.start, resource_size(&res)); | |
101 | if (!pmsu_mp_base) { | |
102 | pr_err("unable to map registers\n"); | |
103 | release_mem_region(res.start, resource_size(&res)); | |
104 | ret = -ENOMEM; | |
105 | goto out; | |
106 | } | |
107 | ||
108 | out: | |
109 | of_node_put(np); | |
110 | return ret; | |
7444dad2 GC |
111 | } |
112 | ||
113 | early_initcall(armada_370_xp_pmsu_init); |