[deliverable/linux.git] / arch / arm / mach-mvebu / pmsu.c

/*
 * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370 and Armada XP SOCs have a power management service
 * unit which is responsible for powering down and waking up CPUs and
 * other SOC units
 */

#define pr_fmt(fmt) "mvebu-pmsu: " fmt

#include <linux/cpu_pm.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mbus.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>
#include "common.h"

static void __iomem *pmsu_mp_base;

#define PMSU_BASE_OFFSET    0x100
#define PMSU_REG_SIZE	    0x1000

/* PMSU MP registers */
#define PMSU_CONTROL_AND_CONFIG(cpu)	    ((cpu * 0x100) + 0x104)
#define PMSU_CONTROL_AND_CONFIG_DFS_REQ		BIT(18)
#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ	BIT(16)
#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN	BIT(20)

#define PMSU_CPU_POWER_DOWN_CONTROL(cpu)    ((cpu * 0x100) + 0x108)

#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP	BIT(0)

#define PMSU_STATUS_AND_MASK(cpu)	    ((cpu * 0x100) + 0x10c)
#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT	BIT(16)
#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT	BIT(17)
#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP		BIT(20)
#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP		BIT(21)
#define PMSU_STATUS_AND_MASK_DBG_WAKEUP		BIT(22)
#define PMSU_STATUS_AND_MASK_IRQ_MASK		BIT(24)
#define PMSU_STATUS_AND_MASK_FIQ_MASK		BIT(25)

#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)

/* PMSU fabric registers */
#define L2C_NFABRIC_PM_CTL		    0x4
#define L2C_NFABRIC_PM_CTL_PWR_DOWN		BIT(20)

#define SRAM_PHYS_BASE  0xFFFF0000
#define BOOTROM_BASE    0xFFF00000
#define BOOTROM_SIZE    0x100000

extern void ll_disable_coherency(void);
extern void ll_enable_coherency(void);

extern void armada_370_xp_cpu_resume(void);

static struct platform_device mvebu_v7_cpuidle_device = {
	.name = "cpuidle-armada-370-xp",
};

static struct of_device_id of_pmsu_table[] = {
	{ .compatible = "marvell,armada-370-pmsu", },
	{ .compatible = "marvell,armada-370-xp-pmsu", },
	{ .compatible = "marvell,armada-380-pmsu", },
	{ /* end of list */ },
};

void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
{
	writel(virt_to_phys(boot_addr), pmsu_mp_base +
		PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
}

extern unsigned char mvebu_boot_wa_start;
extern unsigned char mvebu_boot_wa_end;

/*
 * This function sets up the boot address workaround needed for SMP
 * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
 * BootROM Mbus window, and instead remaps a crypto SRAM into which a
 * custom piece of code is copied to replace the problematic BootROM.
 */
int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
			     unsigned int crypto_eng_attribute,
			     phys_addr_t resume_addr_reg)
{
	void __iomem *sram_virt_base;
	u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;

	mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
	mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
				    SRAM_PHYS_BASE, SZ_64K);

	sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
	if (!sram_virt_base) {
		pr_err("Unable to map SRAM to setup the boot address WA\n");
		return -ENOMEM;
	}

	memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);

	/*
	 * The last word of the code copied in SRAM must contain the
	 * physical base address of the PMSU register. We
	 * intentionally store this address in the native endianness
	 * of the system.
	 */
	__raw_writel((unsigned long)resume_addr_reg,
		     sram_virt_base + code_len - 4);

	iounmap(sram_virt_base);

	return 0;
}

static int __init mvebu_v7_pmsu_init(void)
{
	struct device_node *np;
	struct resource res;
	int ret = 0;

	np = of_find_matching_node(NULL, of_pmsu_table);
	if (!np)
		return 0;

	pr_info("Initializing Power Management Service Unit\n");

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("unable to get resource\n");
		ret = -ENOENT;
		goto out;
	}

	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
		pr_warn(FW_WARN "deprecated pmsu binding\n");
		res.start = res.start - PMSU_BASE_OFFSET;
		res.end = res.start + PMSU_REG_SIZE - 1;
	}

	if (!request_mem_region(res.start, resource_size(&res),
				np->full_name)) {
		pr_err("unable to request region\n");
		ret = -EBUSY;
		goto out;
	}

	pmsu_mp_base = ioremap(res.start, resource_size(&res));
	if (!pmsu_mp_base) {
		pr_err("unable to map registers\n");
		release_mem_region(res.start, resource_size(&res));
		ret = -ENOMEM;
		goto out;
	}

 out:
	of_node_put(np);
	return ret;
}

static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
{
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;

	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
}

/* No locking is needed because we only access per-CPU registers */
static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
{
	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	u32 reg;

	if (pmsu_mp_base == NULL)
		return -EINVAL;

	/*
	 * Adjust the PMSU configuration to wait for WFI signal, enable
	 * IRQ and FIQ as wakeup events, set wait for snoop queue empty
	 * indication and mask IRQ and FIQ from CPU
	 */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |
	       PMSU_STATUS_AND_MASK_IRQ_WAKEUP       |
	       PMSU_STATUS_AND_MASK_FIQ_WAKEUP       |
	       PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
	       PMSU_STATUS_AND_MASK_IRQ_MASK         |
	       PMSU_STATUS_AND_MASK_FIQ_MASK;
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));

	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	/* ask HW to power down the L2 Cache if needed */
	if (deepidle)
		reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;

	/* request power down */
	reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));

	/* Disable snoop disable by HW - SW is taking care of it */
	reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
	writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));

	return 0;
}

int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
{
	int ret;

	ret = mvebu_v7_pmsu_idle_prepare(deepidle);
	if (ret)
		return ret;

	v7_exit_coherency_flush(all);

	ll_disable_coherency();

	dsb();

	wfi();

	/* If we are here, wfi failed. As processors run out of
	 * coherency for some time, tlbs might be stale, so flush them
	 */
	local_flush_tlb_all();

	ll_enable_coherency();

	/* Test the CR_C bit and set it if it was cleared */
	asm volatile(
	"mrc	p15, 0, r0, c1, c0, 0 \n\t"
	"tst	r0, #(1 << 2) \n\t"
	"orreq	r0, r0, #(1 << 2) \n\t"
	"mcreq	p15, 0, r0, c1, c0, 0 \n\t"
	"isb	"
	: : : "r0");

	pr_warn("Failed to suspend the system\n");

	return 0;
}

static int armada_370_xp_cpu_suspend(unsigned long deepidle)
{
	return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
}

/* No locking is needed because we only access per-CPU registers */
void mvebu_v7_pmsu_idle_exit(void)
{
	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;

	/* cancel ask HW to power down the L2 Cache if possible */
	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));

	/* cancel Enable wakeup events and mask interrupts */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
}

static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	if (action == CPU_PM_ENTER) {
		unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
		mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
	} else if (action == CPU_PM_EXIT) {
		mvebu_v7_pmsu_idle_exit();
	}

	return NOTIFY_OK;
}

static struct notifier_block mvebu_v7_cpu_pm_notifier = {
	.notifier_call = mvebu_v7_cpu_pm_notify,
};

static int __init mvebu_v7_cpu_pm_init(void)
{
	struct device_node *np;

	/*
	 * Check that all the requirements are available to enable
	 * cpuidle. So far, it is only supported on Armada XP, cpuidle
	 * needs the coherency fabric and the PMSU enabled
	 */

	if (!of_machine_is_compatible("marvell,armadaxp"))
		return 0;

	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
	if (!np)
		return 0;
	of_node_put(np);

	np = of_find_matching_node(NULL, of_pmsu_table);
	if (!np)
		return 0;
	of_node_put(np);

	mvebu_v7_pmsu_enable_l2_powerdown_onidle();
	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
	platform_device_register(&mvebu_v7_cpuidle_device);
	cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);

	return 0;
}

arch_initcall(mvebu_v7_cpu_pm_init);
early_initcall(mvebu_v7_pmsu_init);
Commit	Line	Data
7444dad2 GC	1	/*
	2	* Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Yehuda Yitschak <yehuday@marvell.com>
	7	* Gregory Clement <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* The Armada 370 and Armada XP SOCs have a power management service
	15	* unit which is responsible for powering down and waking up CPUs and
	16	* other SOC units
	17	*/
	18
bd045a1e TP	19	#define pr_fmt(fmt) "mvebu-pmsu: " fmt
bd045a1e TP	20
d163ee16	21	#include <linux/cpu_pm.h>
7444dad2	22	#include <linux/init.h>
7444dad2	23	#include <linux/io.h>
3e328428	24	#include <linux/kernel.h>
3076cc58	25	#include <linux/mbus.h>
3e328428	26	#include <linux/of_address.h>
8c16babc	27	#include <linux/platform_device.h>
49754ffe	28	#include <linux/resource.h>
3e328428	29	#include <linux/smp.h>
c3e04cab GC	30	#include <asm/cacheflush.h>
c3e04cab GC	31	#include <asm/cp15.h>
7444dad2	32	#include <asm/smp_plat.h>
c3e04cab GC	33	#include <asm/suspend.h>
c3e04cab GC	34	#include <asm/tlbflush.h>
49754ffe	35	#include "common.h"
7444dad2 GC	36
7444dad2 GC	37	static void __iomem *pmsu_mp_base;
7444dad2	38
0c3acc74 GC	39	#define PMSU_BASE_OFFSET 0x100
	40	#define PMSU_REG_SIZE 0x1000
	41
f713c7e7	42	/* PMSU MP registers */
c3e04cab GC	43	#define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
	44	#define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
	45	#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
	46	#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
	47
	48	#define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
	49
	50	#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
	51
	52	#define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
	53	#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
	54	#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
	55	#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
	56	#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
	57	#define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
	58	#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
	59	#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
	60
f713c7e7 GC	61	#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
	62
	63	/* PMSU fabric registers */
	64	#define L2C_NFABRIC_PM_CTL 0x4
	65	#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
7444dad2	66
3076cc58 GC	67	#define SRAM_PHYS_BASE 0xFFFF0000
	68	#define BOOTROM_BASE 0xFFF00000
	69	#define BOOTROM_SIZE 0x100000
	70
c3e04cab GC	71	extern void ll_disable_coherency(void);
	72	extern void ll_enable_coherency(void);
	73
6509dc74 TP	74	extern void armada_370_xp_cpu_resume(void);
6509dc74 TP	75
898ef3e9	76	static struct platform_device mvebu_v7_cpuidle_device = {
8c16babc GC	77	.name = "cpuidle-armada-370-xp",
	78	};
	79
7444dad2	80	static struct of_device_id of_pmsu_table[] = {
0c3acc74 GC	81	{ .compatible = "marvell,armada-370-pmsu", },
0c3acc74 GC	82	{ .compatible = "marvell,armada-370-xp-pmsu", },
b4bca249	83	{ .compatible = "marvell,armada-380-pmsu", },
7444dad2 GC	84	{ /* end of list */ },
	85	};
	86
05ad6906	87	void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
02e7b067 GC	88	{
	89	writel(virt_to_phys(boot_addr), pmsu_mp_base +
	90	PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
	91	}
	92
3076cc58 GC	93	extern unsigned char mvebu_boot_wa_start;
	94	extern unsigned char mvebu_boot_wa_end;
	95
	96	/*
	97	* This function sets up the boot address workaround needed for SMP
	98	* boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
	99	* BootROM Mbus window, and instead remaps a crypto SRAM into which a
	100	* custom piece of code is copied to replace the problematic BootROM.
	101	*/
	102	int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
	103	unsigned int crypto_eng_attribute,
	104	phys_addr_t resume_addr_reg)
	105	{
	106	void __iomem *sram_virt_base;
	107	u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
	108
	109	mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
	110	mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
	111	SRAM_PHYS_BASE, SZ_64K);
	112
	113	sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
	114	if (!sram_virt_base) {
	115	pr_err("Unable to map SRAM to setup the boot address WA\n");
	116	return -ENOMEM;
	117	}
	118
	119	memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
	120
	121	/*
	122	* The last word of the code copied in SRAM must contain the
	123	* physical base address of the PMSU register. We
	124	* intentionally store this address in the native endianness
	125	* of the system.
	126	*/
	127	__raw_writel((unsigned long)resume_addr_reg,
	128	sram_virt_base + code_len - 4);
	129
	130	iounmap(sram_virt_base);
	131
	132	return 0;
	133	}
	134
898ef3e9	135	static int __init mvebu_v7_pmsu_init(void)
7444dad2 GC	136	{
7444dad2 GC	137	struct device_node *np;
bd045a1e TP	138	struct resource res;
bd045a1e TP	139	int ret = 0;
7444dad2 GC	140
7444dad2 GC	141	np = of_find_matching_node(NULL, of_pmsu_table);
bd045a1e TP	142	if (!np)
	143	return 0;
	144
	145	pr_info("Initializing Power Management Service Unit\n");
	146
	147	if (of_address_to_resource(np, 0, &res)) {
	148	pr_err("unable to get resource\n");
	149	ret = -ENOENT;
	150	goto out;
7444dad2 GC	151	}
7444dad2 GC	152
0c3acc74 GC	153	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
	154	pr_warn(FW_WARN "deprecated pmsu binding\n");
	155	res.start = res.start - PMSU_BASE_OFFSET;
	156	res.end = res.start + PMSU_REG_SIZE - 1;
	157	}
	158
bd045a1e TP	159	if (!request_mem_region(res.start, resource_size(&res),
	160	np->full_name)) {
	161	pr_err("unable to request region\n");
	162	ret = -EBUSY;
	163	goto out;
	164	}
	165
	166	pmsu_mp_base = ioremap(res.start, resource_size(&res));
	167	if (!pmsu_mp_base) {
	168	pr_err("unable to map registers\n");
	169	release_mem_region(res.start, resource_size(&res));
	170	ret = -ENOMEM;
	171	goto out;
	172	}
	173
	174	out:
	175	of_node_put(np);
	176	return ret;
7444dad2 GC	177	}
7444dad2 GC	178
898ef3e9	179	static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
f713c7e7 GC	180	{
	181	u32 reg;
	182
	183	if (pmsu_mp_base == NULL)
	184	return;
	185
	186	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
	187	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	188	reg \|= L2C_NFABRIC_PM_CTL_PWR_DOWN;
	189	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	190	}
	191
c3e04cab	192	/* No locking is needed because we only access per-CPU registers */
898ef3e9	193	static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
c3e04cab GC	194	{
	195	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	196	u32 reg;
	197
	198	if (pmsu_mp_base == NULL)
bbb92284	199	return -EINVAL;
c3e04cab GC	200
	201	/*
	202	* Adjust the PMSU configuration to wait for WFI signal, enable
	203	* IRQ and FIQ as wakeup events, set wait for snoop queue empty
	204	* indication and mask IRQ and FIQ from CPU
	205	*/
	206	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	207	reg \|= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT \|
	208	PMSU_STATUS_AND_MASK_IRQ_WAKEUP \|
	209	PMSU_STATUS_AND_MASK_FIQ_WAKEUP \|
	210	PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT \|
	211	PMSU_STATUS_AND_MASK_IRQ_MASK \|
	212	PMSU_STATUS_AND_MASK_FIQ_MASK;
	213	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	214
	215	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	216	/* ask HW to power down the L2 Cache if needed */
	217	if (deepidle)
	218	reg \|= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	219
	220	/* request power down */
	221	reg \|= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
	222	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	223
	224	/* Disable snoop disable by HW - SW is taking care of it */
	225	reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	226	reg \|= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
	227	writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
c3e04cab	228
9ce35884 GC	229	return 0;
	230	}
	231
	232	int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
	233	{
	234	int ret;
	235
898ef3e9	236	ret = mvebu_v7_pmsu_idle_prepare(deepidle);
9ce35884 GC	237	if (ret)
	238	return ret;
	239
c3e04cab GC	240	v7_exit_coherency_flush(all);
	241
	242	ll_disable_coherency();
	243
	244	dsb();
	245
	246	wfi();
	247
	248	/* If we are here, wfi failed. As processors run out of
	249	* coherency for some time, tlbs might be stale, so flush them
	250	*/
	251	local_flush_tlb_all();
	252
	253	ll_enable_coherency();
	254
	255	/* Test the CR_C bit and set it if it was cleared */
	256	asm volatile(
0d461e1b GC	257	"mrc p15, 0, r0, c1, c0, 0 \n\t"
	258	"tst r0, #(1 << 2) \n\t"
	259	"orreq r0, r0, #(1 << 2) \n\t"
	260	"mcreq p15, 0, r0, c1, c0, 0 \n\t"
c3e04cab	261	"isb "
0d461e1b	262	: : : "r0");
c3e04cab GC	263
	264	pr_warn("Failed to suspend the system\n");
	265
	266	return 0;
	267	}
	268
	269	static int armada_370_xp_cpu_suspend(unsigned long deepidle)
	270	{
bbb92284	271	return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
c3e04cab GC	272	}
	273
	274	/* No locking is needed because we only access per-CPU registers */
898ef3e9	275	void mvebu_v7_pmsu_idle_exit(void)
c3e04cab GC	276	{
	277	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	278	u32 reg;
	279
	280	if (pmsu_mp_base == NULL)
	281	return;
	282
	283	/* cancel ask HW to power down the L2 Cache if possible */
	284	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	285	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	286	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	287
	288	/* cancel Enable wakeup events and mask interrupts */
	289	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	290	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP \| PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
	291	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	292	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
	293	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK \| PMSU_STATUS_AND_MASK_FIQ_MASK);
	294	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	295	}
	296
898ef3e9	297	static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
d163ee16 GC	298	unsigned long action, void *hcpu)
	299	{
	300	if (action == CPU_PM_ENTER) {
	301	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	302	mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
	303	} else if (action == CPU_PM_EXIT) {
898ef3e9	304	mvebu_v7_pmsu_idle_exit();
d163ee16 GC	305	}
	306
	307	return NOTIFY_OK;
	308	}
	309
898ef3e9 GC	310	static struct notifier_block mvebu_v7_cpu_pm_notifier = {
898ef3e9 GC	311	.notifier_call = mvebu_v7_cpu_pm_notify,
d163ee16 GC	312	};
d163ee16 GC	313
898ef3e9	314	static int __init mvebu_v7_cpu_pm_init(void)
8c16babc GC	315	{
	316	struct device_node *np;
	317
	318	/*
	319	* Check that all the requirements are available to enable
	320	* cpuidle. So far, it is only supported on Armada XP, cpuidle
	321	* needs the coherency fabric and the PMSU enabled
	322	*/
	323
	324	if (!of_machine_is_compatible("marvell,armadaxp"))
	325	return 0;
	326
	327	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
	328	if (!np)
	329	return 0;
	330	of_node_put(np);
	331
	332	np = of_find_matching_node(NULL, of_pmsu_table);
	333	if (!np)
	334	return 0;
	335	of_node_put(np);
	336
898ef3e9 GC	337	mvebu_v7_pmsu_enable_l2_powerdown_onidle();
	338	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
	339	platform_device_register(&mvebu_v7_cpuidle_device);
	340	cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
8c16babc GC	341
	342	return 0;
	343	}
	344
898ef3e9 GC	345	arch_initcall(mvebu_v7_cpu_pm_init);
898ef3e9 GC	346	early_initcall(mvebu_v7_pmsu_init);