[deliverable/linux.git] / arch / arm / mach-mvebu / pmsu.c

/*
 * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370 and Armada XP SOCs have a power management service
 * unit which is responsible for powering down and waking up CPUs and
 * other SOC units
 */

#define pr_fmt(fmt) "mvebu-pmsu: " fmt

#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/resource.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>
#include "common.h"

static void __iomem *pmsu_mp_base;

#define PMSU_BASE_OFFSET    0x100
#define PMSU_REG_SIZE	    0x1000

/* PMSU MP registers */
#define PMSU_CONTROL_AND_CONFIG(cpu)	    ((cpu * 0x100) + 0x104)
#define PMSU_CONTROL_AND_CONFIG_DFS_REQ		BIT(18)
#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ	BIT(16)
#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN	BIT(20)

#define PMSU_CPU_POWER_DOWN_CONTROL(cpu)    ((cpu * 0x100) + 0x108)

#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP	BIT(0)

#define PMSU_STATUS_AND_MASK(cpu)	    ((cpu * 0x100) + 0x10c)
#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT	BIT(16)
#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT	BIT(17)
#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP		BIT(20)
#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP		BIT(21)
#define PMSU_STATUS_AND_MASK_DBG_WAKEUP		BIT(22)
#define PMSU_STATUS_AND_MASK_IRQ_MASK		BIT(24)
#define PMSU_STATUS_AND_MASK_FIQ_MASK		BIT(25)

#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)

/* PMSU fabric registers */
#define L2C_NFABRIC_PM_CTL		    0x4
#define L2C_NFABRIC_PM_CTL_PWR_DOWN		BIT(20)

extern void ll_disable_coherency(void);
extern void ll_enable_coherency(void);

static struct of_device_id of_pmsu_table[] = {
	{ .compatible = "marvell,armada-370-pmsu", },
	{ .compatible = "marvell,armada-370-xp-pmsu", },
	{ .compatible = "marvell,armada-380-pmsu", },
	{ /* end of list */ },
};

void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
{
	writel(virt_to_phys(boot_addr), pmsu_mp_base +
		PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
}

static int __init armada_370_xp_pmsu_init(void)
{
	struct device_node *np;
	struct resource res;
	int ret = 0;

	np = of_find_matching_node(NULL, of_pmsu_table);
	if (!np)
		return 0;

	pr_info("Initializing Power Management Service Unit\n");

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("unable to get resource\n");
		ret = -ENOENT;
		goto out;
	}

	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
		pr_warn(FW_WARN "deprecated pmsu binding\n");
		res.start = res.start - PMSU_BASE_OFFSET;
		res.end = res.start + PMSU_REG_SIZE - 1;
	}

	if (!request_mem_region(res.start, resource_size(&res),
				np->full_name)) {
		pr_err("unable to request region\n");
		ret = -EBUSY;
		goto out;
	}

	pmsu_mp_base = ioremap(res.start, resource_size(&res));
	if (!pmsu_mp_base) {
		pr_err("unable to map registers\n");
		release_mem_region(res.start, resource_size(&res));
		ret = -ENOMEM;
		goto out;
	}

 out:
	of_node_put(np);
	return ret;
}

static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
{
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;

	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
}

static void armada_370_xp_cpu_resume(void)
{
	asm volatile("bl    ll_add_cpu_to_smp_group\n\t"
		     "bl    ll_enable_coherency\n\t"
		     "b	    cpu_resume\n\t");
}

/* No locking is needed because we only access per-CPU registers */
void armada_370_xp_pmsu_idle_prepare(bool deepidle)
{
	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;

	/*
	 * Adjust the PMSU configuration to wait for WFI signal, enable
	 * IRQ and FIQ as wakeup events, set wait for snoop queue empty
	 * indication and mask IRQ and FIQ from CPU
	 */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |
	       PMSU_STATUS_AND_MASK_IRQ_WAKEUP       |
	       PMSU_STATUS_AND_MASK_FIQ_WAKEUP       |
	       PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
	       PMSU_STATUS_AND_MASK_IRQ_MASK         |
	       PMSU_STATUS_AND_MASK_FIQ_MASK;
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));

	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	/* ask HW to power down the L2 Cache if needed */
	if (deepidle)
		reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;

	/* request power down */
	reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));

	/* Disable snoop disable by HW - SW is taking care of it */
	reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
	writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
}

static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
{
	armada_370_xp_pmsu_idle_prepare(deepidle);

	v7_exit_coherency_flush(all);

	ll_disable_coherency();

	dsb();

	wfi();

	/* If we are here, wfi failed. As processors run out of
	 * coherency for some time, tlbs might be stale, so flush them
	 */
	local_flush_tlb_all();

	ll_enable_coherency();

	/* Test the CR_C bit and set it if it was cleared */
	asm volatile(
	"mrc	p15, 0, %0, c1, c0, 0 \n\t"
	"tst	%0, #(1 << 2) \n\t"
	"orreq	%0, %0, #(1 << 2) \n\t"
	"mcreq	p15, 0, %0, c1, c0, 0 \n\t"
	"isb	"
	: : "r" (0));

	pr_warn("Failed to suspend the system\n");

	return 0;
}

static int armada_370_xp_cpu_suspend(unsigned long deepidle)
{
	return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
}

/* No locking is needed because we only access per-CPU registers */
static noinline void armada_370_xp_pmsu_idle_restore(void)
{
	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;

	/* cancel ask HW to power down the L2 Cache if possible */
	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));

	/* cancel Enable wakeup events and mask interrupts */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
}

static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	if (action == CPU_PM_ENTER) {
		unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
		mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
	} else if (action == CPU_PM_EXIT) {
		armada_370_xp_pmsu_idle_restore();
	}

	return NOTIFY_OK;
}

static struct notifier_block armada_370_xp_cpu_pm_notifier = {
	.notifier_call = armada_370_xp_cpu_pm_notify,
};

early_initcall(armada_370_xp_pmsu_init);
Commit	Line	Data
7444dad2 GC	1	/*
	2	* Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Yehuda Yitschak <yehuday@marvell.com>
	7	* Gregory Clement <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* The Armada 370 and Armada XP SOCs have a power management service
	15	* unit which is responsible for powering down and waking up CPUs and
	16	* other SOC units
	17	*/
	18
bd045a1e TP	19	#define pr_fmt(fmt) "mvebu-pmsu: " fmt
bd045a1e TP	20
d163ee16	21	#include <linux/cpu_pm.h>
7444dad2 GC	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/of_address.h>
	25	#include <linux/io.h>
	26	#include <linux/smp.h>
49754ffe	27	#include <linux/resource.h>
c3e04cab GC	28	#include <asm/cacheflush.h>
c3e04cab GC	29	#include <asm/cp15.h>
7444dad2	30	#include <asm/smp_plat.h>
c3e04cab GC	31	#include <asm/suspend.h>
c3e04cab GC	32	#include <asm/tlbflush.h>
49754ffe	33	#include "common.h"
7444dad2 GC	34
7444dad2 GC	35	static void __iomem *pmsu_mp_base;
7444dad2	36
0c3acc74 GC	37	#define PMSU_BASE_OFFSET 0x100
	38	#define PMSU_REG_SIZE 0x1000
	39
f713c7e7	40	/* PMSU MP registers */
c3e04cab GC	41	#define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
	42	#define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
	43	#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
	44	#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
	45
	46	#define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
	47
	48	#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
	49
	50	#define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
	51	#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
	52	#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
	53	#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
	54	#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
	55	#define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
	56	#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
	57	#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
	58
f713c7e7 GC	59	#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
	60
	61	/* PMSU fabric registers */
	62	#define L2C_NFABRIC_PM_CTL 0x4
	63	#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
7444dad2	64
c3e04cab GC	65	extern void ll_disable_coherency(void);
	66	extern void ll_enable_coherency(void);
	67
7444dad2	68	static struct of_device_id of_pmsu_table[] = {
0c3acc74 GC	69	{ .compatible = "marvell,armada-370-pmsu", },
0c3acc74 GC	70	{ .compatible = "marvell,armada-370-xp-pmsu", },
b4bca249	71	{ .compatible = "marvell,armada-380-pmsu", },
7444dad2 GC	72	{ /* end of list */ },
	73	};
	74
05ad6906	75	void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
02e7b067 GC	76	{
	77	writel(virt_to_phys(boot_addr), pmsu_mp_base +
	78	PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
	79	}
	80
b12634e3	81	static int __init armada_370_xp_pmsu_init(void)
7444dad2 GC	82	{
7444dad2 GC	83	struct device_node *np;
bd045a1e TP	84	struct resource res;
bd045a1e TP	85	int ret = 0;
7444dad2 GC	86
7444dad2 GC	87	np = of_find_matching_node(NULL, of_pmsu_table);
bd045a1e TP	88	if (!np)
	89	return 0;
	90
	91	pr_info("Initializing Power Management Service Unit\n");
	92
	93	if (of_address_to_resource(np, 0, &res)) {
	94	pr_err("unable to get resource\n");
	95	ret = -ENOENT;
	96	goto out;
7444dad2 GC	97	}
7444dad2 GC	98
0c3acc74 GC	99	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
	100	pr_warn(FW_WARN "deprecated pmsu binding\n");
	101	res.start = res.start - PMSU_BASE_OFFSET;
	102	res.end = res.start + PMSU_REG_SIZE - 1;
	103	}
	104
bd045a1e TP	105	if (!request_mem_region(res.start, resource_size(&res),
	106	np->full_name)) {
	107	pr_err("unable to request region\n");
	108	ret = -EBUSY;
	109	goto out;
	110	}
	111
	112	pmsu_mp_base = ioremap(res.start, resource_size(&res));
	113	if (!pmsu_mp_base) {
	114	pr_err("unable to map registers\n");
	115	release_mem_region(res.start, resource_size(&res));
	116	ret = -ENOMEM;
	117	goto out;
	118	}
	119
	120	out:
	121	of_node_put(np);
	122	return ret;
7444dad2 GC	123	}
7444dad2 GC	124
f713c7e7 GC	125	static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
	126	{
	127	u32 reg;
	128
	129	if (pmsu_mp_base == NULL)
	130	return;
	131
	132	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
	133	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	134	reg \|= L2C_NFABRIC_PM_CTL_PWR_DOWN;
	135	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	136	}
	137
c3e04cab GC	138	static void armada_370_xp_cpu_resume(void)
	139	{
	140	asm volatile("bl ll_add_cpu_to_smp_group\n\t"
	141	"bl ll_enable_coherency\n\t"
	142	"b cpu_resume\n\t");
	143	}
	144
	145	/* No locking is needed because we only access per-CPU registers */
	146	void armada_370_xp_pmsu_idle_prepare(bool deepidle)
	147	{
	148	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	149	u32 reg;
	150
	151	if (pmsu_mp_base == NULL)
	152	return;
	153
	154	/*
	155	* Adjust the PMSU configuration to wait for WFI signal, enable
	156	* IRQ and FIQ as wakeup events, set wait for snoop queue empty
	157	* indication and mask IRQ and FIQ from CPU
	158	*/
	159	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	160	reg \|= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT \|
	161	PMSU_STATUS_AND_MASK_IRQ_WAKEUP \|
	162	PMSU_STATUS_AND_MASK_FIQ_WAKEUP \|
	163	PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT \|
	164	PMSU_STATUS_AND_MASK_IRQ_MASK \|
	165	PMSU_STATUS_AND_MASK_FIQ_MASK;
	166	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	167
	168	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	169	/* ask HW to power down the L2 Cache if needed */
	170	if (deepidle)
	171	reg \|= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	172
	173	/* request power down */
	174	reg \|= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
	175	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	176
	177	/* Disable snoop disable by HW - SW is taking care of it */
	178	reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	179	reg \|= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
	180	writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	181	}
	182
	183	static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
	184	{
	185	armada_370_xp_pmsu_idle_prepare(deepidle);
	186
	187	v7_exit_coherency_flush(all);
	188
	189	ll_disable_coherency();
	190
	191	dsb();
	192
	193	wfi();
	194
	195	/* If we are here, wfi failed. As processors run out of
	196	* coherency for some time, tlbs might be stale, so flush them
	197	*/
	198	local_flush_tlb_all();
	199
	200	ll_enable_coherency();
	201
202	/* Test the CR_C bit and set it if it was cleared */
203	asm volatile(
204	"mrc p15, 0, %0, c1, c0, 0 \n\t"
205	"tst %0, #(1 << 2) \n\t"
206	"orreq %0, %0, #(1 << 2) \n\t"
207	"mcreq p15, 0, %0, c1, c0, 0 \n\t"
208	"isb "
209	: : "r" (0));
210
211	pr_warn("Failed to suspend the system\n");
212
213	return 0;
214	}
215
216	static int armada_370_xp_cpu_suspend(unsigned long deepidle)
217	{
218	return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
219	}
220
221	/* No locking is needed because we only access per-CPU registers */
222	static noinline void armada_370_xp_pmsu_idle_restore(void)
223	{
224	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
225	u32 reg;
226
227	if (pmsu_mp_base == NULL)
228	return;
229
230	/* cancel ask HW to power down the L2 Cache if possible */
231	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
232	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
233	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
234
235	/* cancel Enable wakeup events and mask interrupts */
236	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
237	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP \| PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
238	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
239	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
240	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK \| PMSU_STATUS_AND_MASK_FIQ_MASK);
241	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
242	}
243
d163ee16 GC	244	static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
	245	unsigned long action, void *hcpu)
	246	{
	247	if (action == CPU_PM_ENTER) {
	248	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	249	mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
	250	} else if (action == CPU_PM_EXIT) {
	251	armada_370_xp_pmsu_idle_restore();
	252	}
	253
	254	return NOTIFY_OK;
	255	}
	256
	257	static struct notifier_block armada_370_xp_cpu_pm_notifier = {
	258	.notifier_call = armada_370_xp_cpu_pm_notify,
	259	};
	260
7444dad2	261	early_initcall(armada_370_xp_pmsu_init);