projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6509dc74 TP |
1 | /* |
| 2 | * Copyright (C) 2014 Marvell | |
| 3 | * | |
| 4 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
| 5 | * Gregory Clement <gregory.clement@free-electrons.com> | |
| 6 | * | |
| 7 | * This file is licensed under the terms of the GNU General Public | |
| 8 | * License version 2. This program is licensed "as is" without any | |
| 9 | * warranty of any kind, whether express or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/linkage.h> | |
| 13 | #include <asm/assembler.h> | |
| 14 | ||
| f746ac32 GC |
15 | |
| 16 | ENTRY(armada_38x_scu_power_up) | |
| 17 | mrc p15, 4, r1, c15, c0 @ get SCU base address | |
| 18 | orr r1, r1, #0x8 @ SCU CPU Power Status Register | |
| 19 | mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID | |
| 20 | and r0, r0, #15 | |
| 21 | add r1, r1, r0 | |
| 22 | mov r0, #0x0 | |
| 23 | strb r0, [r1] @ switch SCU power state to Normal mode | |
| 24 | ret lr | |
| 25 | ENDPROC(armada_38x_scu_power_up) | |
| 26 | ||
| 6509dc74 TP |
27 | /* |
| 28 | * This is the entry point through which CPUs exiting cpuidle deep | |
| 29 | * idle state are going. | |
| 30 | */ | |
| 31 | ENTRY(armada_370_xp_cpu_resume) | |
| 32 | ARM_BE8(setend be ) @ go BE8 if entered LE | |
| 77ea46d1 TP |
33 | /* |
| 34 | * Disable the MMU that might have been enabled in BootROM if | |
| 35 | * this code is used in the resume path of a suspend/resume | |
| 36 | * cycle. | |
| 37 | */ | |
| 38 | mrc p15, 0, r1, c1, c0, 0 | |
| 39 | bic r1, #1 | |
| 40 | mcr p15, 0, r1, c1, c0, 0 | |
| 6509dc74 TP |
41 | bl ll_add_cpu_to_smp_group |
| 42 | bl ll_enable_coherency | |
| 43 | b cpu_resume | |
| 44 | ENDPROC(armada_370_xp_cpu_resume) | |
| 45 | ||
| e53b1fd4 GC |
46 | ENTRY(armada_38x_cpu_resume) |
| 47 | /* do we need it for Armada 38x*/ | |
| 48 | ARM_BE8(setend be ) @ go BE8 if entered LE | |
| 49 | bl v7_invalidate_l1 | |
| f746ac32 | 50 | bl armada_38x_scu_power_up |
| e53b1fd4 GC |
51 | b cpu_resume |
| 52 | ENDPROC(armada_38x_cpu_resume) | |
| 53 | ||
| 3076cc58 GC |
54 | .global mvebu_boot_wa_start |
| 55 | .global mvebu_boot_wa_end | |
| 56 | ||
| 57 | /* The following code will be executed from SRAM */ | |
| 58 | ENTRY(mvebu_boot_wa_start) | |
| 59 | mvebu_boot_wa_start: | |
| 60 | ARM_BE8(setend be) | |
| 61 | adr r0, 1f | |
| 62 | ldr r0, [r0] @ load the address of the | |
| 63 | @ resume register | |
| 64 | ldr r0, [r0] @ load the value in the | |
| 65 | @ resume register | |
| 66 | ARM_BE8(rev r0, r0) @ the value is stored LE | |
| 67 | mov pc, r0 @ jump to this value | |
| 68 | /* | |
| 69 | * the last word of this piece of code will be filled by the physical | |
| 70 | * address of the boot address register just after being copied in SRAM | |
| 71 | */ | |
| 72 | 1: | |
| 73 | .long . | |
| 74 | mvebu_boot_wa_end: | |
| 75 | ENDPROC(mvebu_boot_wa_end) |