[deliverable/linux.git] / arch / arm / mach-mvebu / system-controller.c

/*
 * System controller support for Armada 370, 375 and XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370, 375 and Armada XP SoCs have a range of
 * miscellaneous registers, that do not belong to a particular device,
 * but rather provide system-level features. This basic
 * system-controller driver provides a device tree binding for those
 * registers, and implements utility functions offering various
 * features related to those registers.
 *
 * For now, the feature set is limited to restarting the platform by a
 * soft-reset, but it might be extended in the future.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/reboot.h>
#include "common.h"

static void __iomem *system_controller_base;

struct mvebu_system_controller {
	u32 rstoutn_mask_offset;
	u32 system_soft_reset_offset;

	u32 rstoutn_mask_reset_out_en;
	u32 system_soft_reset;

	u32 resume_boot_addr;

	u32 dev_id;
	u32 rev_id;
};
static struct mvebu_system_controller *mvebu_sc;

static const struct mvebu_system_controller armada_370_xp_system_controller = {
	.rstoutn_mask_offset = 0x60,
	.system_soft_reset_offset = 0x64,
	.rstoutn_mask_reset_out_en = 0x1,
	.system_soft_reset = 0x1,
	.dev_id = 0x38,
	.rev_id = 0x3c,
};

static const struct mvebu_system_controller armada_375_system_controller = {
	.rstoutn_mask_offset = 0x54,
	.system_soft_reset_offset = 0x58,
	.rstoutn_mask_reset_out_en = 0x1,
	.system_soft_reset = 0x1,
	.resume_boot_addr = 0xd4,
	.dev_id = 0x38,
	.rev_id = 0x3c,
};

static const struct mvebu_system_controller orion_system_controller = {
	.rstoutn_mask_offset = 0x108,
	.system_soft_reset_offset = 0x10c,
	.rstoutn_mask_reset_out_en = 0x4,
	.system_soft_reset = 0x1,
};

static const struct of_device_id of_system_controller_table[] = {
	{
		.compatible = "marvell,orion-system-controller",
		.data = (void *) &orion_system_controller,
	}, {
		.compatible = "marvell,armada-370-xp-system-controller",
		.data = (void *) &armada_370_xp_system_controller,
	}, {
		.compatible = "marvell,armada-375-system-controller",
		.data = (void *) &armada_375_system_controller,
	},
	{ /* end of list */ },
};

void mvebu_restart(enum reboot_mode mode, const char *cmd)
{
	if (!system_controller_base) {
		pr_err("Cannot restart, system-controller not available: check the device tree\n");
	} else {
		/*
		 * Enable soft reset to assert RSTOUTn.
		 */
		writel(mvebu_sc->rstoutn_mask_reset_out_en,
			system_controller_base +
			mvebu_sc->rstoutn_mask_offset);
		/*
		 * Assert soft reset.
		 */
		writel(mvebu_sc->system_soft_reset,
			system_controller_base +
			mvebu_sc->system_soft_reset_offset);
	}

	while (1)
		;
}

int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
{
	if (of_machine_is_compatible("marvell,armada380") &&
		system_controller_base) {
		*dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
		*rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
			& 0xF;
		return 0;
	} else
		return -ENODEV;
}

#ifdef CONFIG_SMP
void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
{
	BUG_ON(system_controller_base == NULL);
	BUG_ON(mvebu_sc->resume_boot_addr == 0);
	writel(virt_to_phys(boot_addr), system_controller_base +
	       mvebu_sc->resume_boot_addr);
}
#endif

static int __init mvebu_system_controller_init(void)
{
	const struct of_device_id *match;
	struct device_node *np;

	np = of_find_matching_node_and_match(NULL, of_system_controller_table,
					     &match);
	if (np) {
		system_controller_base = of_iomap(np, 0);
		mvebu_sc = (struct mvebu_system_controller *)match->data;
		of_node_put(np);
	}

	return 0;
}

early_initcall(mvebu_system_controller_init);
Commit	Line	Data
31af49db	1	/*
df863de1	2	* System controller support for Armada 370, 375 and XP platforms.
31af49db GC	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
df863de1	14	* The Armada 370, 375 and Armada XP SoCs have a range of
31af49db GC	15	* miscellaneous registers, that do not belong to a particular device,
	16	* but rather provide system-level features. This basic
	17	* system-controller driver provides a device tree binding for those
	18	* registers, and implements utility functions offering various
	19	* features related to those registers.
	20	*
	21	* For now, the feature set is limited to restarting the platform by a
	22	* soft-reset, but it might be extended in the future.
	23	*/
	24
	25	#include <linux/kernel.h>
	26	#include <linux/init.h>
	27	#include <linux/of_address.h>
	28	#include <linux/io.h>
7b6d864b	29	#include <linux/reboot.h>
b12634e3	30	#include "common.h"
31af49db GC	31
	32	static void __iomem *system_controller_base;
	33
	34	struct mvebu_system_controller {
	35	u32 rstoutn_mask_offset;
	36	u32 system_soft_reset_offset;
	37
	38	u32 rstoutn_mask_reset_out_en;
	39	u32 system_soft_reset;
00504be4 GC	40
00504be4 GC	41	u32 resume_boot_addr;
9674d4a3 GC	42
	43	u32 dev_id;
	44	u32 rev_id;
31af49db GC	45	};
	46	static struct mvebu_system_controller *mvebu_sc;
	47
b12634e3	48	static const struct mvebu_system_controller armada_370_xp_system_controller = {
31af49db GC	49	.rstoutn_mask_offset = 0x60,
	50	.system_soft_reset_offset = 0x64,
	51	.rstoutn_mask_reset_out_en = 0x1,
	52	.system_soft_reset = 0x1,
9674d4a3 GC	53	.dev_id = 0x38,
9674d4a3 GC	54	.rev_id = 0x3c,
31af49db GC	55	};
31af49db GC	56
df863de1 TP	57	static const struct mvebu_system_controller armada_375_system_controller = {
	58	.rstoutn_mask_offset = 0x54,
	59	.system_soft_reset_offset = 0x58,
	60	.rstoutn_mask_reset_out_en = 0x1,
	61	.system_soft_reset = 0x1,
00504be4	62	.resume_boot_addr = 0xd4,
9674d4a3 GC	63	.dev_id = 0x38,
9674d4a3 GC	64	.rev_id = 0x3c,
df863de1 TP	65	};
df863de1 TP	66
b12634e3	67	static const struct mvebu_system_controller orion_system_controller = {
31af49db GC	68	.rstoutn_mask_offset = 0x108,
	69	.system_soft_reset_offset = 0x10c,
	70	.rstoutn_mask_reset_out_en = 0x4,
	71	.system_soft_reset = 0x1,
	72	};
	73
a8cacc0a	74	static const struct of_device_id of_system_controller_table[] = {
31af49db GC	75	{
	76	.compatible = "marvell,orion-system-controller",
	77	.data = (void *) &orion_system_controller,
	78	}, {
	79	.compatible = "marvell,armada-370-xp-system-controller",
	80	.data = (void *) &armada_370_xp_system_controller,
df863de1 TP	81	}, {
	82	.compatible = "marvell,armada-375-system-controller",
	83	.data = (void *) &armada_375_system_controller,
31af49db GC	84	},
	85	{ /* end of list */ },
	86	};
	87
7b6d864b	88	void mvebu_restart(enum reboot_mode mode, const char *cmd)
31af49db GC	89	{
	90	if (!system_controller_base) {
	91	pr_err("Cannot restart, system-controller not available: check the device tree\n");
	92	} else {
	93	/*
	94	* Enable soft reset to assert RSTOUTn.
	95	*/
	96	writel(mvebu_sc->rstoutn_mask_reset_out_en,
	97	system_controller_base +
	98	mvebu_sc->rstoutn_mask_offset);
	99	/*
	100	* Assert soft reset.
	101	*/
	102	writel(mvebu_sc->system_soft_reset,
	103	system_controller_base +
	104	mvebu_sc->system_soft_reset_offset);
	105	}
	106
	107	while (1)
	108	;
	109	}
	110
9674d4a3 GC	111	int mvebu_system_controller_get_soc_id(u32 dev, u32 rev)
	112	{
	113	if (of_machine_is_compatible("marvell,armada380") &&
	114	system_controller_base) {
	115	*dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
	116	*rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
	117	& 0xF;
	118	return 0;
	119	} else
	120	return -ENODEV;
	121	}
	122
00504be4 GC	123	#ifdef CONFIG_SMP
	124	void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
	125	{
	126	BUG_ON(system_controller_base == NULL);
	127	BUG_ON(mvebu_sc->resume_boot_addr == 0);
	128	writel(virt_to_phys(boot_addr), system_controller_base +
	129	mvebu_sc->resume_boot_addr);
	130	}
	131	#endif
	132
31af49db GC	133	static int __init mvebu_system_controller_init(void)
31af49db GC	134	{
a8cacc0a	135	const struct of_device_id *match;
31af49db GC	136	struct device_node *np;
31af49db GC	137
a8cacc0a JC	138	np = of_find_matching_node_and_match(NULL, of_system_controller_table,
a8cacc0a JC	139	&match);
31af49db	140	if (np) {
31af49db GC	141	system_controller_base = of_iomap(np, 0);
31af49db GC	142	mvebu_sc = (struct mvebu_system_controller *)match->data;
abe511ac	143	of_node_put(np);
31af49db GC	144	}
	145
	146	return 0;
	147	}
	148
00504be4	149	early_initcall(mvebu_system_controller_init);