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1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__ | |
21 | #define __ARCH_ARM_MACH_MX2_CRM_REGS_H__ | |
22 | ||
23 | #include <mach/hardware.h> | |
24 | ||
25 | /* Register offsets */ | |
26 | #define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) | |
27 | #define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) | |
28 | #define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) | |
29 | #define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) | |
30 | #define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) | |
31 | #define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) | |
32 | #define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) | |
33 | #define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) | |
34 | #define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) | |
35 | #define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) | |
36 | #define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) | |
37 | #define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) | |
38 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) | |
39 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) | |
40 | ||
41 | #define CCM_CSCR_PRESC_OFFSET 29 | |
42 | #define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) | |
43 | ||
44 | #define CCM_CSCR_USB_OFFSET 26 | |
45 | #define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) | |
46 | #define CCM_CSCR_SD_OFFSET 24 | |
47 | #define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) | |
48 | #define CCM_CSCR_SPLLRES (1 << 22) | |
49 | #define CCM_CSCR_MPLLRES (1 << 21) | |
50 | #define CCM_CSCR_SSI2_OFFSET 20 | |
51 | #define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) | |
52 | #define CCM_CSCR_SSI1_OFFSET 19 | |
53 | #define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) | |
54 | #define CCM_CSCR_FIR_OFFSET 18 | |
55 | #define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) | |
56 | #define CCM_CSCR_SP (1 << 17) | |
57 | #define CCM_CSCR_MCU (1 << 16) | |
58 | #define CCM_CSCR_BCLK_OFFSET 10 | |
59 | #define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) | |
60 | #define CCM_CSCR_IPDIV_OFFSET 9 | |
61 | #define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) | |
62 | ||
63 | #define CCM_CSCR_OSC26MDIV (1 << 4) | |
64 | #define CCM_CSCR_OSC26M (1 << 3) | |
65 | #define CCM_CSCR_FPM (1 << 2) | |
66 | #define CCM_CSCR_SPEN (1 << 1) | |
67 | #define CCM_CSCR_MPEN 1 | |
68 | ||
69 | ||
70 | ||
71 | #define CCM_MPCTL0_CPLM (1 << 31) | |
72 | #define CCM_MPCTL0_PD_OFFSET 26 | |
73 | #define CCM_MPCTL0_PD_MASK (0xf << 26) | |
74 | #define CCM_MPCTL0_MFD_OFFSET 16 | |
75 | #define CCM_MPCTL0_MFD_MASK (0x3ff << 16) | |
76 | #define CCM_MPCTL0_MFI_OFFSET 10 | |
77 | #define CCM_MPCTL0_MFI_MASK (0xf << 10) | |
78 | #define CCM_MPCTL0_MFN_OFFSET 0 | |
79 | #define CCM_MPCTL0_MFN_MASK 0x3ff | |
80 | ||
81 | #define CCM_MPCTL1_LF (1 << 15) | |
82 | #define CCM_MPCTL1_BRMO (1 << 6) | |
83 | ||
84 | #define CCM_SPCTL0_CPLM (1 << 31) | |
85 | #define CCM_SPCTL0_PD_OFFSET 26 | |
86 | #define CCM_SPCTL0_PD_MASK (0xf << 26) | |
87 | #define CCM_SPCTL0_MFD_OFFSET 16 | |
88 | #define CCM_SPCTL0_MFD_MASK (0x3ff << 16) | |
89 | #define CCM_SPCTL0_MFI_OFFSET 10 | |
90 | #define CCM_SPCTL0_MFI_MASK (0xf << 10) | |
91 | #define CCM_SPCTL0_MFN_OFFSET 0 | |
92 | #define CCM_SPCTL0_MFN_MASK 0x3ff | |
93 | ||
94 | #define CCM_SPCTL1_LF (1 << 15) | |
95 | #define CCM_SPCTL1_BRMO (1 << 6) | |
96 | ||
97 | #define CCM_OSC26MCTL_PEAK_OFFSET 16 | |
98 | #define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) | |
99 | #define CCM_OSC26MCTL_AGC_OFFSET 8 | |
100 | #define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) | |
101 | #define CCM_OSC26MCTL_ANATEST_OFFSET 0 | |
102 | #define CCM_OSC26MCTL_ANATEST_MASK 0x3f | |
103 | ||
104 | #define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 | |
105 | #define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) | |
106 | #define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 | |
107 | #define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) | |
108 | #define CCM_PCDR0_NFCDIV_OFFSET 12 | |
109 | #define CCM_PCDR0_NFCDIV_MASK (0xf << 12) | |
110 | #define CCM_PCDR0_48MDIV_OFFSET 5 | |
111 | #define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) | |
112 | #define CCM_PCDR0_FIRIDIV_OFFSET 0 | |
113 | #define CCM_PCDR0_FIRIDIV_MASK 0x1f | |
114 | #define CCM_PCDR1_PERDIV4_OFFSET 24 | |
115 | #define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) | |
116 | #define CCM_PCDR1_PERDIV3_OFFSET 16 | |
117 | #define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) | |
118 | #define CCM_PCDR1_PERDIV2_OFFSET 8 | |
119 | #define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) | |
120 | #define CCM_PCDR1_PERDIV1_OFFSET 0 | |
121 | #define CCM_PCDR1_PERDIV1_MASK 0x3f | |
122 | ||
123 | #define CCM_PCCR_HCLK_CSI_OFFSET 31 | |
124 | #define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 | |
125 | #define CCM_PCCR_HCLK_DMA_OFFSET 30 | |
126 | #define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 | |
127 | #define CCM_PCCR_HCLK_BROM_OFFSET 28 | |
128 | #define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 | |
129 | #define CCM_PCCR_HCLK_EMMA_OFFSET 27 | |
130 | #define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 | |
131 | #define CCM_PCCR_HCLK_LCDC_OFFSET 26 | |
132 | #define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 | |
133 | #define CCM_PCCR_HCLK_SLCDC_OFFSET 25 | |
134 | #define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 | |
135 | #define CCM_PCCR_HCLK_USBOTG_OFFSET 24 | |
136 | #define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 | |
137 | #define CCM_PCCR_HCLK_BMI_OFFSET 23 | |
138 | #define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) | |
139 | #define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 | |
140 | #define CCM_PCCR_PERCLK4_OFFSET 22 | |
141 | #define CCM_PCCR_PERCLK4_REG CCM_PCCR0 | |
142 | #define CCM_PCCR_SLCDC_OFFSET 21 | |
143 | #define CCM_PCCR_SLCDC_REG CCM_PCCR0 | |
144 | #define CCM_PCCR_FIRI_BAUD_OFFSET 20 | |
145 | #define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) | |
146 | #define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 | |
147 | #define CCM_PCCR_NFC_OFFSET 19 | |
148 | #define CCM_PCCR_NFC_REG CCM_PCCR0 | |
149 | #define CCM_PCCR_LCDC_OFFSET 18 | |
150 | #define CCM_PCCR_LCDC_REG CCM_PCCR0 | |
151 | #define CCM_PCCR_SSI1_BAUD_OFFSET 17 | |
152 | #define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 | |
153 | #define CCM_PCCR_SSI2_BAUD_OFFSET 16 | |
154 | #define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 | |
155 | #define CCM_PCCR_EMMA_OFFSET 15 | |
156 | #define CCM_PCCR_EMMA_REG CCM_PCCR0 | |
157 | #define CCM_PCCR_USBOTG_OFFSET 14 | |
158 | #define CCM_PCCR_USBOTG_REG CCM_PCCR0 | |
159 | #define CCM_PCCR_DMA_OFFSET 13 | |
160 | #define CCM_PCCR_DMA_REG CCM_PCCR0 | |
161 | #define CCM_PCCR_I2C1_OFFSET 12 | |
162 | #define CCM_PCCR_I2C1_REG CCM_PCCR0 | |
163 | #define CCM_PCCR_GPIO_OFFSET 11 | |
164 | #define CCM_PCCR_GPIO_REG CCM_PCCR0 | |
165 | #define CCM_PCCR_SDHC2_OFFSET 10 | |
166 | #define CCM_PCCR_SDHC2_REG CCM_PCCR0 | |
167 | #define CCM_PCCR_SDHC1_OFFSET 9 | |
168 | #define CCM_PCCR_SDHC1_REG CCM_PCCR0 | |
169 | #define CCM_PCCR_FIRI_OFFSET 8 | |
170 | #define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) | |
171 | #define CCM_PCCR_FIRI_REG CCM_PCCR0 | |
172 | #define CCM_PCCR_SSI2_IPG_OFFSET 7 | |
173 | #define CCM_PCCR_SSI2_REG CCM_PCCR0 | |
174 | #define CCM_PCCR_SSI1_IPG_OFFSET 6 | |
175 | #define CCM_PCCR_SSI1_REG CCM_PCCR0 | |
176 | #define CCM_PCCR_CSPI2_OFFSET 5 | |
177 | #define CCM_PCCR_CSPI2_REG CCM_PCCR0 | |
178 | #define CCM_PCCR_CSPI1_OFFSET 4 | |
179 | #define CCM_PCCR_CSPI1_REG CCM_PCCR0 | |
180 | #define CCM_PCCR_UART4_OFFSET 3 | |
181 | #define CCM_PCCR_UART4_REG CCM_PCCR0 | |
182 | #define CCM_PCCR_UART3_OFFSET 2 | |
183 | #define CCM_PCCR_UART3_REG CCM_PCCR0 | |
184 | #define CCM_PCCR_UART2_OFFSET 1 | |
185 | #define CCM_PCCR_UART2_REG CCM_PCCR0 | |
186 | #define CCM_PCCR_UART1_OFFSET 0 | |
187 | #define CCM_PCCR_UART1_REG CCM_PCCR0 | |
188 | ||
189 | #define CCM_PCCR_OWIRE_OFFSET 31 | |
190 | #define CCM_PCCR_OWIRE_REG CCM_PCCR1 | |
191 | #define CCM_PCCR_KPP_OFFSET 30 | |
192 | #define CCM_PCCR_KPP_REG CCM_PCCR1 | |
193 | #define CCM_PCCR_RTC_OFFSET 29 | |
194 | #define CCM_PCCR_RTC_REG CCM_PCCR1 | |
195 | #define CCM_PCCR_PWM_OFFSET 28 | |
196 | #define CCM_PCCR_PWM_REG CCM_PCCR1 | |
197 | #define CCM_PCCR_GPT3_OFFSET 27 | |
198 | #define CCM_PCCR_GPT3_REG CCM_PCCR1 | |
199 | #define CCM_PCCR_GPT2_OFFSET 26 | |
200 | #define CCM_PCCR_GPT2_REG CCM_PCCR1 | |
201 | #define CCM_PCCR_GPT1_OFFSET 25 | |
202 | #define CCM_PCCR_GPT1_REG CCM_PCCR1 | |
203 | #define CCM_PCCR_WDT_OFFSET 24 | |
204 | #define CCM_PCCR_WDT_REG CCM_PCCR1 | |
205 | #define CCM_PCCR_CSPI3_OFFSET 23 | |
206 | #define CCM_PCCR_CSPI3_REG CCM_PCCR1 | |
207 | ||
208 | #define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) | |
209 | #define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) | |
210 | #define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) | |
211 | #define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) | |
212 | #define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) | |
213 | #define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) | |
214 | #define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) | |
215 | #define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) | |
216 | #define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) | |
217 | #define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) | |
218 | #define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) | |
219 | #define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) | |
220 | #define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) | |
221 | #define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) | |
222 | #define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) | |
223 | #define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) | |
224 | #define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) | |
225 | #define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) | |
226 | #define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) | |
227 | #define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) | |
228 | #define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) | |
229 | #define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) | |
230 | #define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) | |
231 | #define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) | |
232 | #define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) | |
233 | #define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) | |
234 | #define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) | |
235 | #define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) | |
236 | #define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) | |
237 | #define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) | |
238 | #define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) | |
239 | #define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) | |
240 | #define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) | |
241 | #define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) | |
242 | #define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) | |
243 | #define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) | |
244 | #define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) | |
245 | ||
246 | ||
247 | #define CCM_CCSR_32KSR (1 << 15) | |
248 | ||
249 | #define CCM_CCSR_CLKMODE1 (1 << 9) | |
250 | #define CCM_CCSR_CLKMODE0 (1 << 8) | |
251 | ||
252 | #define CCM_CCSR_CLKOSEL_OFFSET 0 | |
253 | #define CCM_CCSR_CLKOSEL_MASK 0x1f | |
254 | ||
255 | #define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ | |
256 | #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ | |
257 | ||
258 | #endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ |